Workshop on Novel Designs for RISC-V Cores and Peripheral IPs (NIPS) Program

Jaume Abella, BSC

Kajetan Nürnberger, Infineon Technologies

Quintauris (tbc.)

Speaker and Author: Sergi Alcaide, Barcelona Supercomputing Center (BSC)

Co-Authors: Juan Carlos Rodriguez, Marc Grau i Fornt, Ahlame el Afghani, Francisco Fuentes, Jaume Abella, Barcelona Supercomputing Center (BSC)

Abstract: In this presentation, we will cover and explain why new Safety-Critical MPSoCs require the use of Safety Islands together with HPC components. Following this line, we will present the work that HPES has been carrying out and show the results obtained and components developed.

Speaker and Author: J. Parker Jones, TUWien

Co-Author: Daniel Mueller-Gritschneder, TUWien

Abstract: With the ever increasing computing demands for embedded systems, there is a need for a flexible platform which enables exploration of the application of vector architectures in embedded environments.  In order to fill this niche, we present Vicuna 2.0, a highly configurable vector co-processor which supports the embedded subsets of the RISCV Vector Specification implemented in synthesizable SystemVerilog. With support for the Core-V eXtension InterFace (CV-X-IF), the co-processor can be connected to any main core which provides support for this interface.  Vicuna2.0 has a many configurable features that are well suited for design space exploration for embedded systems: vector register size, throughput per functional unit, parallel execution of functional units via parallel pipelines, and support for multiple parallel vector data ports.  Additionally, we have extended Vicuna 2.0 with a "Custom Functional Unit" interface to allow for the rapid deployment of custom vector functional units with no required changes to the vector processor itself.  Finally, all improvements, upgrades, and new functional units follow the design principles of the original Vicuna project, meaning the co-processor is free of timing anomalies and is suitable for use in timing predictable systems.   We plan to continue development of Vicuna2.0, and utilize it to explore the application of vector architectures to novel embedded workloads.

Eleni Politi, Harokopio University of Athens

Ana Rísquez Navarro, Fentiss

Johannes Ecker, Infineon Technologies

Johannes Geier, Technical University Munich

Natalie Simson 1,2), Lucas Hennig 1,2), Mohamed Badawy 1,2), Ares Tahiraga 1), Johannes Ecker 1,2), Wolfgang Ecker 1,2) 

1) Infineon Technologies, 2) Technical University Munich

Speaker and Author: Alexandru Drimbarean, Fotonation

Co-Author: Honorius Galmeanu, Fotonation

Abstract: Edge AI demands high performance under tight power, latency, and cost constraints — beyond what general-purpose RISC-V cores can deliver. This talk presents PCNN, FotoNation's programmable CNN accelerator from the EU Chips-JU ISOLDE project, paired with its co-designed compiler and runtime. A scalable MAC array (256–2048 MACs/cycle) with concurrent Arithmetic/Load/Save modules integrates into any RISC-V SoC via standard AXI4/APB interfaces, no custom ISA needed. Hazard-aware compiler scheduling cuts inference latency by over 20%, achieving >90% MAC utilization and >10x speedup over a RISC-V CPU baseline on FPGA-validated vision workloads — demonstrating co-design as the key to efficient edge intelligence.

Ares Tahiraga, Infineon Technologies

Robert Kunzelmann, Infineon Technologies

Speaker: Andrei Albu, Politecnico di Torino, IT

Co-Authors: Giovanni Pollo, Mohamed Amine Hamdi, Andrei Albu, Sara Vinco, Alessio Burrello, Daniele Jahier Pagliari, Politecnico di Torino, IT

Abstract: Instruction Set Simulators (ISSs) are fundamental to enable full-system simulation and Design Space Exploration (DSE), but they are not sufficient to cover the heterogeneity and complexity of modern Cyber-Physical Systems (CPS). This talk introduces MESSY, an open-source virtual platform for RISC-V CPSs that wraps GVSoC (or alternative ISSs) and enhances its functionality in three directions. First, it permits accurate modelling of non-functional properties such as timing and power, as well as components such as batteries and harvesters, exploiting SystemC/AMS flexible modelling abstractions. Second, it permits coupling or replacing software ISSs with hardware emulation on FPGAs for cycle-accurate yet fast prototyping of specific components, through a minimally invasive JTAG-based protocol. Third, it can be integrated with world simulators, to enable in-context prototyping of applications for which modelling interactions with the surrounding environment is fundamental (e.g., in the robotics domain). We will conclude the talk with demonstrations of concrete applications of MESSY in the context of the TRISTAN and RIGOLETTO projects.

Presenter: M. Ulbricht 2)

Authors: K. Hannemann 1), L. Luchterhandt 1), W. Müller 1), J. Scheytt 1), M. Ulbricht 2), L. Lu 2)

1)  Paderborn University, 2) IHP

Fatma Jebali, CEA