Talk A.2: Vicuna2.0: A Flexible Platform for Design Space Exploration for Embedded Vector Processors
Speaker and Author: J. Parker Jones, TUWien
Co-Author: Daniel Mueller-Gritschneder, TUWien
Abstract: With the ever increasing computing demands for embedded systems, there is a need for a flexible platform which enables exploration of the application of vector architectures in embedded environments. In order to fill this niche, we present Vicuna 2.0, a highly configurable vector co-processor which supports the embedded subsets of the RISCV Vector Specification implemented in synthesizable SystemVerilog. With support for the Core-V eXtension InterFace (CV-X-IF), the co-processor can be connected to any main core which provides support for this interface. Vicuna2.0 has a many configurable features that are well suited for design space exploration for embedded systems: vector register size, throughput per functional unit, parallel execution of functional units via parallel pipelines, and support for multiple parallel vector data ports. Additionally, we have extended Vicuna 2.0 with a "Custom Functional Unit" interface to allow for the rapid deployment of custom vector functional units with no required changes to the vector processor itself. Finally, all improvements, upgrades, and new functional units follow the design principles of the original Vicuna project, meaning the co-processor is free of timing anomalies and is suitable for use in timing predictable systems. We plan to continue development of Vicuna2.0, and utilize it to explore the application of vector architectures to novel embedded workloads.
