Workshop on Novel Designs for RISC-V Cores and Peripheral IPs (NIPS) Programm

Jaume Abella, BSC

Kajetan Nürnberger, Infineon Technologies

Abstract: The automotive industry is in the middle of a transformation of the car compute architecture. The talk will address the different opportunities this change will bring. Like the needs for tailored and tiny controllers for endpoints, the need for higher performing microcontroller in the  zone and domain controllers and the wish to create flexible composable real time software.

Quintauris (tbc.)

Speaker and Author: Sergi Alcaide, Barcelona Supercomputing Center (BSC)

Co-Authors: Juan Carlos Rodriguez, Marc Grau i Fornt, Ahlame el Afghani, Francisco Fuentes, Jaume Abella, Barcelona Supercomputing Center (BSC)

Abstract: In this presentation, we will cover and explain why new Safety-Critical MPSoCs require the use of Safety Islands together with HPC components. Following this line, we will present the work that HPES has been carrying out and show the results obtained and components developed.

Speaker and Author: J. Parker Jones, TUWien

Co-Author: Daniel Mueller-Gritschneder, TUWien

Abstract: With the ever increasing computing demands for embedded systems, there is a need for a flexible platform which enables exploration of the application of vector architectures in embedded environments.  In order to fill this niche, we present Vicuna 2.0, a highly configurable vector co-processor which supports the embedded subsets of the RISCV Vector Specification implemented in synthesizable SystemVerilog. With support for the Core-V eXtension InterFace (CV-X-IF), the co-processor can be connected to any main core which provides support for this interface.  Vicuna2.0 has a many configurable features that are well suited for design space exploration for embedded systems: vector register size, throughput per functional unit, parallel execution of functional units via parallel pipelines, and support for multiple parallel vector data ports.  Additionally, we have extended Vicuna 2.0 with a "Custom Functional Unit" interface to allow for the rapid deployment of custom vector functional units with no required changes to the vector processor itself.  Finally, all improvements, upgrades, and new functional units follow the design principles of the original Vicuna project, meaning the co-processor is free of timing anomalies and is suitable for use in timing predictable systems.   We plan to continue development of Vicuna2.0, and utilize it to explore the application of vector architectures to novel embedded workloads.

Speaker: Eleni Politi, Harokopio University of Athens

Co-Authors: Alexandros Dimopoulos, Angelos Maroudis, George Dimitrakopoulos, Harokopio University of Athens

Abstract: Future automotive systems are evolving toward increasingly intelligent and software-defined platforms, where advanced perception, decision-making, and autonomous functions are shaped by increasingly demanding trade-offs between functional capability, computational efficiency, responsiveness and safety.. As the complexity of AI-enabled workloads in automotive functions continues to grow, simply increasing computational capacity is neither scalable nor sustainable. Instead, future systems require new approaches that achieve higher degrees of intelligence with fewer computational resources.

This talk explores innovative algorithmic approaches for reducing demand by minimizing the number of executed instructions, thereby improving execution efficiency while increasing the intelligence and autonomy of future automotive systems, with particular emphasis on their implementation on RISC-V-based architectures. Approaches such as lightweight and adaptive AI, intelligent task allocation, context-aware processing, and dynamic optimization can enable complex automotive functions to be executed more efficiently by processing only the absolutely necessary information, at the right time, and on the most appropriate computing resource.

Drawing on research and developments from ongoing European projects, including RIGOLETTO and TURANDOT, the presentation discusses how software-hardware co-design can support resource-efficient AI for next-generation automotive applications. Particular attention is given to the interaction between intelligent software, reusable RISC-V hardware and software IP, and heterogeneous edge computing resources.

Finally, the talk discusses the implications of this transition for future automotive RISC-V platforms and highlights the need for closer co-design between intelligent algorithms, software, instruction-set architectures, and hardware, enabling a new generation of automotive computing systems capable of delivering greater intelligence per instruction, per watt, and per computing resource.

Ana Rísquez Navarro, Fentiss

Speaker and Author: Johannes Ecker, Infineon Technologies AG

Co-Authors: Natalie Simson 1,2), Endri Kaja 1), Ralf Brederlow 2), Wolfgang Ecker 1,2)
1) Infineon Technologies AG, 2) TU München

Abstract: Energy efficiency is a central design objective for emerging paradigms, including IoT, Edge AI, and neuromorphic systems. In conventional synchronous circuits, substantial effort is devoted to reducing power consumption; however, the global clock distribution network often remains a major source of energy overhead. Asynchronous circuit design provides a compelling alternative by replacing the global clock with local handshake-based control, enabling activity-driven operation and potentially improved energy efficiency. This presentation discusses practical insights gained from the design of an asynchronous RISC-V processor, with emphasis on architectural implications, design methodology, and implementation challenges. It also examines the conceptual shift required when moving from synchronous timing assumptions to asynchronous design principles

Speaker and Author: Johannes Geier, Technical University Munich

Co-Authors: Philipp van Kempen 1), Conrad Foik 1), Daniel Mueller-Gritschneder 2), Ulf Schlichtmann 1)
1) Technical University of Munich, 2) TU Wien

Abstract: Application-specific instruction set processors (ASIPs) offer a way to tailor computation to a workload, but effective specialization requires design choices at two levels: the instruction set and the microarchitecture. The benefit of an instruction-set extension depends on its behavior as well as the pipeline, memory system, and branch prediction mechanisms that govern execution. Performance-driven processor design, therefore, calls for methods that support exploration across both levels.
This talk presents a design-space exploration methodology built around our tools for processor description, generation, and simulation. Starting from CoreDSL and ETISS, we introduce two complementary dimensions of flexibility. At the ISA level, we discuss behavioral instruction descriptions and the development of application-specific extensions, illustrated by GenIE. At the microarchitectural level, we introduce CorePerfDSL as a language for describing performance-relevant properties, including pipelines, caches, and branch prediction. Simulator-based use cases demonstrate how such descriptions can be applied to evaluate architectural alternatives.
The focus is on the interplay of these tools: how behavioral and microarchitectural descriptions contribute to performance evaluation, and how the resulting insights can guide processor specialization. By connecting ISA-level flexibility with microarchitectural exploration, the talk outlines a path from application requirements to informed architectural decisions in the generation of ASIPs.

Speaker: Natalie Simson, Infineon Technologies AG and Technical University Munich

Co-Autors: Lucas Hennig 1,2), Mohamed Badawy 1,2), Ares Tahiraga 1), Johannes Ecker 1,2), Wolfgang Ecker 1,2)

1) Infineon Technologies AG, 2) Technical University Munich

Abstract: This contribution presents lessons learned from designing RISC-V cores and SoC components at the Communication and Computation Level (CCL), a design abstraction positioned between RTL and IP-/SoC-component level. CCL builds on the principle of separating communication from computation and uses the Timed Handshake-Based Design (THS) discipline to make synchronization, data movement, and computation explicit throughout the design process. While these concepts are individually well established in digital design, their systematic and consistent application enables a different way of structuring microarchitectures and reasoning about implementation trade-offs. The talk introduces the core concepts of CCL and THS, discusses how conventional microarchitectural structures evolve under this design discipline, and illustrates the approach using several RISC-V CPU implementations. Quantitative power, performance, and area (PPA) comparisons with conventional RTL implementations are used to assess the practical impact of CCL and THS and to highlight opportunities for more modular, analyzable, and scalable digital design.

Speaker and Author: Alexandru Drimbarean, Fotonation

Co-Author: Honorius Galmeanu, Fotonation

Abstract: Edge AI demands high performance under tight power, latency, and cost constraints — beyond what general-purpose RISC-V cores can deliver. This talk presents PCNN, FotoNation's programmable CNN accelerator from the EU Chips-JU ISOLDE project, paired with its co-designed compiler and runtime. A scalable MAC array (256–2048 MACs/cycle) with concurrent Arithmetic/Load/Save modules integrates into any RISC-V SoC via standard AXI4/APB interfaces, no custom ISA needed. Hazard-aware compiler scheduling cuts inference latency by over 20%, achieving >90% MAC utilization and >10x speedup over a RISC-V CPU baseline on FPGA-validated vision workloads — demonstrating co-design as the key to efficient edge intelligence.

Speaker: Endri Kaja, Infineon Technologies AG

Authors: Robert Kunzelman, Paritosh Kumar Sinha, Natalie Simson, Endri Kaja, Sebastian Prebeck, Wolfgang Ecker, Infineon Technologies AG

Abstract: As part of the ISOLDE project, we are releasing a set of open source infrastructure IPs designed to accelerate SoC development and foster an open hardware ecosystem. The current portfolio includes a Timer, an Interrupt Controller, and a Bus Matrix, providing the essential building blocks required to assemble a functional embedded system around a processor core. All IPs are developed using the MetaRTL-based generation methodology and the Universal Specification Format (USF) for verification, enabling a high degree of automation. Together, these components form a reusable system foundation onto which users can integrate their preferred RISC-V processor and application-specific peripherals. By providing a ready-to-use infrastructure subsystem, the listed open source IPs lower the barrier to RISC-V hardware innovation.

Speaker and Author: Robert Kunzelmann, Infineon Technologies AG

Co-Authors: Anton Paule, FZI Research Center for Information Technology; Johannes Geier, Technical University of Munich; Stefan Wallentowitz, Munich University of Applied Sciences; Wolfgang Ecker, Infineon Technologies AG, Technical University of Munich; Ulf Schlichtmann, Technical University of Munich

Abstract: Integrating reusable semiconductor IP remains a largely manual and error-prone task: structural compatibility and compliance with a nominal standard do not, by themselves, ensure correct protocol behavior and integration. This talk presents DI-FITS, a funded BMFTR 1) project that aims to establish an open-source methodology for seamless IP integration based on formal behavioral interface specifications. We will outline the envisioned DI-FITS flow, spanning IP specification, compatibility checking, and adapter generation. The talk will focus in particular on FITS-IR, the intermediate representation used to formally capture IP interface protocols. It will discuss the technical requirements that shape FITS-IR and propose a layered specification format designed to express interfaces and protocols at multiple levels of abstraction and granularity.

1) Federal Ministry of Research, Technology and Space

Speaker: Andrei Albu, Politecnico di Torino, IT

Co-Authors: Giovanni Pollo, Mohamed Amine Hamdi, Andrei Albu, Sara Vinco, Alessio Burrello, Daniele Jahier Pagliari, Politecnico di Torino, IT

Abstract: Instruction Set Simulators (ISSs) are fundamental to enable full-system simulation and Design Space Exploration (DSE), but they are not sufficient to cover the heterogeneity and complexity of modern Cyber-Physical Systems (CPS). This talk introduces MESSY, an open-source virtual platform for RISC-V CPSs that wraps GVSoC (or alternative ISSs) and enhances its functionality in three directions. First, it permits accurate modelling of non-functional properties such as timing and power, as well as components such as batteries and harvesters, exploiting SystemC/AMS flexible modelling abstractions. Second, it permits coupling or replacing software ISSs with hardware emulation on FPGAs for cycle-accurate yet fast prototyping of specific components, through a minimally invasive JTAG-based protocol. Third, it can be integrated with world simulators, to enable in-context prototyping of applications for which modelling interactions with the surrounding environment is fundamental (e.g., in the robotics domain). We will conclude the talk with demonstrations of concrete applications of MESSY in the context of the TRISTAN and RIGOLETTO projects.

Speaker and Author: Markus Ulbricht 2)

Co-Authors: Kai Arne Hannemann 1), Lars Luchterhandt 1), Wolfgang Müller 1), Li Lu 2), Markus Ulbricht 2)

1)  Paderborn University, 2) IHP

Abstract: Resilient systems require monitoring and prediction of environmental and intrinsic conditions, and the ability to adapt to environmental hazards and optimize the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open source RocketChip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes.

Speaker and Author: Fatma Jebali, CEA List

Co-Authors: Ilmo Gourdin, Daniel Xavier Martin, Caaliph Andriamisaina, CEA List

Abstract: Early-stage HW/SW co-design demands fast yet accurate performance estimation, a balance that remains difficult to achieve with existing simulation approaches. Accurate simulators, when available, enable the automated derivation of higher-level abstractions that preserve fidelity while predicting extra-functional properties, including performance and power, thereby significantly accelerating tasks like software analysis and design space exploration. This talk presents an automated methodology for generating Machine Learning (ML)-based performance models from cycle-accurate simulations and integrating them into fast Instruction Set Simulators (ISS). The approach leverages execution traces to learn the relationship between instruction-level behavior and performance, enabling accurate timing estimation with minimal simulation overhead. By bridging detailed simulation and high-speed execution, the proposed framework provides an efficient solution for early-stage software performance analysis and iterative system design. The talk showcases validation results on the CVA6 architecture, achieving accurate predictions with substantial speedups, and highlights directions to enhance robustness and generalization.