Tuesday, 05.May 2026

08:00 - 09:00

Registration ADTC & edaWorkshop26

On this website you find the ADTC & edaWorkshop26 program, which you can expand individually for each session. There you will find the schedule, the presentation titles, and the speakers. If additional information such as a summary, a CV, or other information is provided, a corresponding link will be displayed under the presentation title.

09:00 - 10:30

Keynote-Session

Moderator: Ulf Schlichtmann (edacentrum)

09:00

Welcome

09:15

CMOS 2.0

Julien Ryckaert (IMEC) 

10:00

Professors introduce their research

10:30 - 11:00

Coffee Break

11:00 - 12:30

Technical Session: AI based tools in chip design

Moderator: Ovidiu Vermesan (SINTEF)

11:00

EDA AI – Lowering the Barrier to Silicon

Thomas Heurung (Siemens EDA)

11:30

A ML-Assisted physical design flow

Husni Habal (Infineon Technologies)

12:00

ST Nano Edge Studio on AI4EDA

NN (ST Nano Edge Studio)

12:30 - 14:30

Lunch and Poster Session

14:30 - 15:50

Expanding the European RISC-V Ecosystem

Moderator: Patrick Pype (NXP) & Holger Schmidt (Infineon Technologies)

14:30

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Jörg Walter (OFFIS, ISOLDE)

14:50

Control Path Fault Analysis in RSIC-V based DNN Accelerator

Saleh Mulhem (U Lübeck, ISOLDE) 

15:10

C-Trace: An Open-Source RISC-V Trace Encoder and its Ecosystem

Albert Schulz (Accemic Technologies, TRISTAN)

15:30

An energy efficient CVA6 RISC-V processor with LPDDR4X Controller+PHY in GF22FDX+ technology

Klaus Hofmann (TU Darmstadt, TRISTAN)

15:50 - 16:15

Coffee Break and Poster Session

16:15 - 17:45

Session on Silicon Photonics

Moderator: Ulf Schlichtmann (edacentrum)

16:15

Project Starlight on Silicon photonics (title pending)

Sylvie Gellida (Starlight)

16:45

Presentation on silicon photonics, title not yet fixed

NN

17:15

Scaling Integrated Photonics: from one-to-many markets

Abdul Rahim (Photondelta)

17:45 - 19:00

Break

19:00 - 22:00

Social Event

18:45

Walk together from Hotel to location (Hilton, Salon Europa)

19:00

Welcome and conferment EDA Achievement Award 2026

19:30 - 22:00

Dinner

Wednesday, 06.May 2026

08:00 - 09:00

Registration ADTC & edaWorkshop26

09:00 - 11:00

Welcome Address BMFTR and Technical Session on IPCEI

Session together with Chipdesign Germany Forum

09:00

BMFTR Welcome Address

09:20

IPCEI – Shaping the Future of Microelectronics Innovation in Europe

Moderator: Patrick Pype (NXP)

Important Projects of Common European Interest (IPCEIs) play a vital role in strengthening European value chains and supporting the Union’s main political goals, such as the Green Deal and Digital Strategy, while also advancing sovereignty.

IPCEIs complement other research and development programs - including EFECS, Eureka, Chips JU, and Horizon Europe - by adding “First Industrial Deployment” (FID) activities to traditional R&D&I efforts.

Currently, IPCEI ME/CT (Microelectronics and Communication Technologies) represents the largest IPCEI to date, with an €8 billion funding budget and about €14 billion in private investment, involving 14 Member States and over 600 companies.

The IPCEI ME/CT program includes 4 workstreams and a spillover activity. The work-streams corresponding to the complementary technical objectives along the microelectronics value chain are: (1) sense, (2) think, (3) communicate and (4) act with spillover as an additional key activity.

Presentations of the IPCEI community:

  • Introduction – what is an IPCEI?
  • Looking forward, research and development communities - including students and PhD candidates - will be key in driving progress for future IPCEIs. Priority research areas will be presented based on current findings of the IPCEI ME/CT in the different workstreams. The following schedule is planned:
    • 9:20: Ferdinand Bell, NXP Semiconductors: ”Current and future view on Important Projects of Common European Interest (IPCEI)”
    • 9:40: Thomas Roedle, Infineon Technologies: “Infineon RF GaN-on-Silicon, a European high-performance, cost-efficient technology for RF power applications”
    • 10:00: Carl Henning Cabos, NXP Semiconductors: “Bosch ECU Demonstrator with NXP S32N7”
    • 10:20: Norbert Thyssen, Infineon Technologies: “Smart Power solutions enabling AI”
    • 10:40: Tomáš Bort, Mycroft Mind: “Grid Intelligence: Bridging the current IPCEI ME/CT and the future IPCEI AST"
11:00 - 11:30

Coffee break and Poster Session

11:30 - 13:00

Session on 3D technology, chiplets and advanced packaging

Moderator: Patrick Cogez (AENEAS)

11:30

Challenges on High Performance Compute scalable designs

Gilberto Rodríguez (Openchip) 

12:00

Presentation (not yet set)

Bartek Kozicki (IMEC) 

12:30

Chiplet-based Hardware Architectures for Software-defined Vehicles

Felix Springer (Bosch)

13:00 - 14:30

Lunch and Poster Session

14:30 - 16:00

Panel: Chips Act 2, Euro CDP, DETs and other Initiatives from Brussels

Panelists from Industry, academia and application exchange their ideas. 

14:30

Panel discussion on Euro CDP, DETs and other Initiatives from Brussels under the Chips Act

Abstract: 
Europe’s semiconductor ambitions are increasingly shaped not by a single instrument, but by a growing set of support mechanisms initiated by Brussels to implement the European Chips Act, such as the Chips for Europe Initiative, the European chip design platform and Design Enablement Teams (DETs), competence centres, and related funding and industrial policy measures. Together, these instruments are intended to strengthen Europe’s technological base, its design and manufacturing capabilities and further on accelerate innovation, improve resilience across the semiconductor value chain, and create better conditions for innovation, scale-up and industrial deployment.

This panel will give an overview of the current policy landscape and discuss what these initiatives mean in practice for industry, SMEs and RTOs. It will explore the technological priorities and market trends Europe should focus on to build competitiveness, strengthen strategic capabilities, and secure a strong position in the global semiconductor ecosystem.

Panelists: 

  • Michael Gude (Cologne Chip)
  • Patrick Pype (NXP)
  • Gilberto Rodríguez (Openchip)
  • Helio Fernandez Tellez (IMEC)
  • Roberto Zafalon (STM)
  • Arian Zwegers (DG CNECT)
     
16:00 - 16:45

Keynote Session: Quantum processors based on trapped ions

Keynote Session together with Chipdesign Germany Forum

16:00

Quantum processors based on trapped ions

Christian Ospelkaus (U Hannover)

Abstract:

Quantum computers have the potential to solve important problems in optimization, materials science, pharmacology, logistics, chemistry, cryptography, artificial intelligence, and other fields that are fundamentally intractable for classical computers at relevant problem scales. A leading physical implementation of quantum bits, or qubits, is based on trapped atomic ions. I will present the underlying system architecture and discuss the design and fabrication of microstructured quantum processors for trapped ions, drawing on techniques borrowed from CMOS and MEMS technologies. The presentation concludes with an overview of the current state of the technology and its remaining challenges.

16:45 - 17:30

Farewell Coffee

16:45

Chipdesign Germany Forum Continuation

On May 6, 2026, the Chipdesign Germany Forum will be in parallel to ADTC and edaWorkshop, starting at 9:00 up to a social event in the evening of May 6. On May 7 it continues the whole day. 
Further information see Website

16:45

Chipdesign Germany Forum 2026

Postersession of Chipdesigen Germany Forum 

19:30

Chipdesign Germany Networking Event