ESWEEK Workshop: Breaking News from EU-Research and Innovation Projects: Novel ways of designing RISC-V Cores and Peripheral-IPs

Workshop Motivation

The workshop will showcase technical innovations from various European projects such as TRISTAN, ISOLDE, RIGOLETTO, and TURANDOT as well as national projects like FITS, Scale4Edge, and SoC HUB, and other ongoing activities. RISC-V continues to be of great interest in Europe. With innovation and product development taking center stage, this workshop complements the research-oriented ESWEEK. Barcelona is one of the European hotspots for RISC-V research and development; the first RISC-V Summit Europe was also held there in June 2023.

Workshop Description

The workshop provides a brief overview of completed and ongoing funded projects, together with innovative technical developments and key lessons learned, as well as the motivation behind the need for new design methods arising from project experience. Topics covered include the organization and provision of intellectual property (requirements, procedures for joint assessments, ease of use), new methods, and use cases:

• IP repositories, hardware IP cards, and software IP cards to simplify selection and ensure continuity and sustainability; (r)evolution of existing formalisms such as IP-XACT or RDF and IP characterization;
• Experience with Chisel, SpinalHDL, and other generator languages and approaches; automation beyond RTL (high-level synthesis, domain-specific automation, etc.); and the opportunities and challenges of cross-RISC-V core reuse;
• Use cases for RISC-V IP, peripheral IP, communications IP, and non-RTL IP development and reuse
• Challenges encountered across projects and outlook on future EU research priorities and ecosystem development

Contributions very welcome

We welcome authors to submit manuscripts on work pertinent to novel methods in designing, validating, packaging, and using IPs with a focus on – but not limited to – RISC-V, CPU-near peripherals and accelerators, and IPs for Systems and Sub-Systems. Ideas and solutions are welcome as well as case studies and learnings from using RISC-V and other IPs.

The organizers strive to publish selected contributions in a book. Discussions with Springer have already started. Please send a proposal with title and abstract to Andreas Vörg <voerg@edacentrum.de>.

Potential Schedule

A possible schedule could look like this, but it must be adapted to the ESWEEK guidelines. Regular talks (approx. 20 minutes) and poster presentations (approx. 5 minutes) are planned.
08:30-10:00    Introduction, 2 invited talks + 6 poster pitches    1:30h 
10:00-11:00    Coffee, Poster Session with 6x Poster    1:00h 
11:00-12:30    Technical Session A, 4 Talks    1:30h
12:30-14:00    Lunch Break    1:30h
14:00-15:30    Technical Session B, 3 Talks + 6 Pitches    1:30h
15:30-16:30    Coffee, Poster Session with 6x Poster    1:00h 
16:30-18:00    Technical Session C, 4 Talks,    1:30h

Dissemination Plans

Selected papers shall be published in a Springer Book (preferred) or Journal. A joint publication with other ESWEEK workshops is also feasible.

Organizers

Jaume Abella    jaume.abella@bsc.es

Jaume Abella is Director of the high performance embedded systems laboratory. At the moment he serves as ESWEEK Conference and Local Co-Chair. Jaume is silently helping as he is also Chair of the ESWEEK

Elena Politi    politie@hua.gr

Elena Politi is a postdoctoral researcher in the Department of Informatics and Telematics at Harokopio University of Athens. She earned her Ph.D. in 2025 and also holds a B.Sc. in Physics from the National and Kapodistrian University of Athens, as well as an M.Sc. in Telecommunication Networks and Telematic Services from Harokopio University, graduating with distinction and receiving an excellence award. Her research focuses on next-generation IoT and edge computing applications, intelligent transportation systems, and AI-enabled optimization algorithms for autonomous vehicles. Since 2018, she has been actively engaged in proposal writing and has served as a project manager in numerous EU-funded projects, including Horizon Europe, covering a wide range of sectors such as transport and mobility, manufacturing, health, and energy.

George Dimitrakopoulos    gdimitra@hua.gr

Wolfgang Ecker    wolfgang.ecker@infineon.com

Wolfgang Ecker is a Distinguished Engineer at Infineon Technologies and a Professor at the Technical University of Munich. His research and innovation focus on digital system modeling, digital design automation, SoC architectures, embedded AI, and AI for design automation.

Wolfgang Ecker has published over 250 technical articles, received seven publication awards, and was honored with the German EDA Achievement Award. He is a member of Acatech, the German Academy of Science and Engineering, and was a member of the German Federal Government's AI Inquiry Commission.

In recent years, Wolfgang Ecker co-organized the RVF – the RISCV and RUST Firmware Workshop held in Tampere, Munich, and Vienna. This year a forth RVF-Workhop is in plan with NORCAS in Tampere. Information on the 3rd RVF workshop can be found at https://www.edacentrum.de/en/rvf