University Booth at DATE 2005

8 - 10th of March 2005, Munich/ Germany

• Program Day 1
• Program Day 2
• Program Day 3
• Descriptions

Program Day 1

Program as PDF File (1500 Kb).

12.00 - 14.00: Asynchronous synthesis and verification
Danil Sokolov: BESST tool kit
University of Newcastle upon Tyne: The BESST tool kit is used for asynchronous system synthesis based on Petri Nets. It incorporates software tools for high-level partitioning, scheduling, direct mapping and logic synthesis. These are used to generate efficient speed-independent circuits from behavioural Verilog specification.
Frank Burns: BESST tool kit – VERISYN and PN2DC
University of Newcastle upon Tyne: High-level scheduling and splitting the system into control and data paths, using Petri Nets for intermediate representation (VeriSyn tool). Direct mapping of control and data path Petri Nets into circuit (PN2DCs tool).
Danil Sokolov: BESST tool kit – OPTIMIST VERIMAP
University of Newcastle upon Tyne: Direct mapping of the control path from Signal Transition Graphs aimed at latency reduction (OptiMist tool). Synthesis of data path blocks with security features (VeriMap tool).
Alex Bystrov: BESST tool kit – CONFRES and VERISAT
University of Newcastle upon Tyne: Logic synthesis of the control path from Signal Transition Graphs (ConfRes and VeriSAT tools), interfaced to Petrify (Technical University of Catalonia).
David Slogsnat / Matthias Harter: SCDF / METAL
See description in “System solution”

14.00 – 16.00: High level simulation, qualification and debug
Richard Buchmann: SystemCASS
Pierre et Marie Curie University: SystemC based simulators are efficient to validate hardware specifications but its performances are not good enough to write and debug embedded software. In this demonstration, we present a new SystemC simulator up to 10x faster by focusing on the cycle accurate simulation level.
Christian Genz: SyCE – SystemC Environment
Universität Bremen: We present a system design environment for SystemC called SyCE. It consists of several components for efficient analysis, verification and debugging of SystemC designs.
Franco Fummi: HSN Co-simulation tool
Universita` di Verona: The software allows to model the hardware, software and network parts of a system and simulate them together (co-simulate) in order to obtain useful data about it’s behavior. The description of each single part can be defined inside the tool’s IDE or imported from outside.
Amr T. Abdel-Hamid: IPWM
Concordia University: The tool is based on a new approach for watermarking IP designs. It embeds the ownership proof as part of the IP design’s FSM. The approach utilizes coinciding as well as un-used transitions in the state transition graph of the design. Such approach increases the robustness of the watermark and allows the development of the first public-key IP watermarking scheme at the FSM level.

16.00 – 18.00: Formal verification techniques
Ali Habibi: SC-VERIFIER
Concordia University: SystemCVerifier tool allows the verification of SystemC designs through a transformation to AsmL. It performs model checking of the design and automatic generation of PSL assertion monitors.
Ingo Schäfer: tudapc – Bounded Model Checker Using Property Based Automated Abstractions
Technische Universität Darmstadt: Bounded Model Checking (BMC) offers the possibility to proof the correctness of an implementation of a digital hardware system. To enhance the capabilities, abstraction techniques were developed. This contribution introduces an experimental software called tudapc applying automatic abstraction techniques to BMC.
Franco Fummi: PCC – Property Coverage Checker
Universita di Verona: PCC is a tool to evaluate the quality of the model checking process. In particular, it estimates the degree of incompleteness of a set of formal properties that have been defined to verify the correctness of an HDL description with respect to the specification.
Roland J. Weiss: SymC – Bounded Property Checking
Universität Tübingen: The formal verification tool SymC combines bounded property checking and symbolic traversal by image computation. It takes properties and a system description as inputs and translates it into a symbolically simulatable representation. SymC traverses the design and the properties simultaneously and observes the state of the properties and reports success or failure of the verification task.
David Slogsnat / Matthias Harter: SCDF / METAL
See description in “System solution”
Christian Genz: SyCE – SystemC Environment
See description in “High level simulation, qualification and debug”

Program Day 2

10.00 – 12.00: System exploration I
Jianjiang Zeng: Micro-profiler
RWTH Aachen University: This work presents a novel profiling technique to guide designers of customized processors for embedded application(s). The profiler can be used to extract micro-architectural and instruction set properties that can speed up the execution of the applications intended to run on the processors.
Masaharu Imai: ASIP Meister – An ASIP Design Environment
Osaka University: „ASIP Meister“ is an Application Specific Instruction-set Processor design environment, which generates both synthesizable HDL description of a designed processor, and its software development tools including an assembler, compiler, and an instruction set simulator to explore a huge design space in a short time.
Toshihiko Hashinaga: Redefis / Vulcan – A SoC Design Platform
Kyushu University: Vulcan is the processor with a reconfigurable data path. It realizes high performance to use application-specific instruction set. We assume the system consisting of Vulcan with a general purpose core processor such as an ARM, Vulcan executes the portions of the application that would run too slowly if implemented on the core processor. It allows efficient user-guided exploration and flexibility analysis for heterogeneous multi-processor embedded systems. Both approaches are realized based on the fast SymTA/S analysis framework and guide the user during the optimization of large systems.
Arne Hamann: SymTA/S
Technische Universität Braunschweig: The presented software allows efficient user-guided exploration and flexibility analysis for heterogeneous multi-processor embedded systems. Both approaches are realized based on the fast SymTA/S analysis framework and guide the user during the optimization of large systems.
David Slogsnat / Matthias Harter: SCDF / METAL
See description in “System solution”

12.00 – 14.00: System exploration II
Andreas Schallenberg: OSSS+R – Cycle-accurate simulation of object oriented descriptions for runtime-reconfigurable systems
Carl von Ossietzky Universität Oldenburg: The approach presented here named OSSS+R extends OSSS with capabilities to model, simulate and synthesize reconfigurable architectures. Simulation capabilities are demonstrated at the booth.
Horst Salzwedel: MLDesigner – Mission Level Designof Electronic Systems
Ilmenau Technical University: Examples of an integrated design flow will be demonstrated, that include simulation of the mission or operational level, performance simulation of executable specifications, functional level simulation, code generation, software performance estimation and validation in overall performance model and hardware-in-the-loop simulation. Additionally process simulations of design and quality-in-design processes, organizational processes and production processes will be demonstrated. The demonstrations will be done with the tool MLDesigner, tool extensions and couplings with other tools.
Zhonghai Lu: NNSE – Nostrum Network-on-Chip Simulation Environment
Royal Institute of Technology in Sweden: A main challenge for Network-on-chip (NoC) design is to select a network architecture that suits a particular application. NNSE allows the user to analyze the performance impact of NoC configuration parameters. It allows one to (1) configure a network with respect to topology, flow control and routing algorithm etc.; (2) configure various regular and application specific traffic patterns; (3) evaluate the network with the traffic patterns in terms of latency and throughput.
Jim Harkin: DIESEL
University of Ulster: ProculTech’s DIESEL training environment facilitates advanced collaborative access and control of remotely based embedded systems hardware, test-debug instrumentation and embedded software design tools through a web based client/server architecture.
David Slogsnat / Matthias Harter: SCDF / METAL
See description in “System solution”

14.00 – 16.00: System solution
Christophe Bobda: ESM – Erlangen Slot Machine
The ESM is a flexible and easy to use FPGA-based hardware platform for dynamic runtime reconfiguration which allows to efficiently implement a wide array of problems, in particular video streaming algorithms and robustness in fault tolerant systems.
Andreas Schallenberg: OSSS+R – Cycle-accurate simulation of object oriented descriptions for runtime-reconfigurable systems
See description in “System exploration II”
David Slogsnat: SCDF – Semi Custom Design Flow
University of Mannheim: A lecture system for graduate students will be presented. Worldwide operating partners like IBM and Toshiba ask for students with this qualification. It has been used to design the ATOLL chip including the ATOLLD software. It to enables 1000 nodes of high performance processors cooperating in a cluster through a network to find tracks of high energy particles.
Matthias Harter: METAL – Automated metal interconnectstructure generation
University of Mannheim: The software consists of a setup of parasitic extraction tools and a script, written in the Cadence SKILL language, to automatically generate 3D metal interconnect structures, to perform parasitic extraction with all of the tools and to store the parasitic values in a file for analysis. The analysis then provides information about the different tool performance and accuracy.
Christian Genz: SyCE – SystemC Environment
See description in “High level simulation, qualification and debug”

16.00 – 18.00: Digital high-level synthesis
Frédéric Pétrot: DSG – Disydent System Generator
Institut National Polytecnique de Grenoble: It is a new addition in Disydent and allows to generate user defined mapping in a simple manner: all implementation details are taken care of by the generation tool, leaving to the designer a small set of system level and not implementation level choices. The generated system is a set of files than run under SystemC using the cycle accurate, bit accurate, simulation models of the SocLib library.
Peeter Ellervee: xTractor – An Academic High-Level Synthesis Toolfor Control and Memory Intensive Applications
Tallinn University of Technology: xTractor is an academic high-level synthesis tool for control and memory intensive applications. The tool has been built up in a modular manner to allow fast and flexible modifications of algorithms and components. Such a tool is needed to teach the students details of synthesis methodologies.
Federico Angiolini: SUNMAP / xpipes – NoC Synthesis Flow
Università di Bologna: A complete NoC synthesis flow. Given the task graph of a target application, SUNMAP maps bandwidth requirements onto a proper topology interconnecting the IP cores. The fabric is instantiated with xpipes NoC components. The resulting system can be simulated with cycle-accuracy. The generated NoC is synthesizable.
Pierre Bomel: GAUT – High-Level Synthesis of Digital Signal Processors
Université de Bretagne Sud: GAUT is a high-level synthesis tool dedicated for DSPs. GAUT generates a pipelined architecture implementing the VHDL-expressed DSP function under sampling, system clock frequency, memory architecture, I/O schedule and target technology constraints.

Program Day 3

10.00 – 12.00: Power and Energy
Jianjiang Zeng: Micro-profiler
See description in “System solution”
Pierre Bomel: SoftExplorer
Université de Bretagne Sud: TheSoftExplorer is an automatic tool that allows the user to estimate the Power/Energy consumption of an application (C and/or ASM code) executed on a given target (Digital Signal Processor or General Purpose Processor). This tool gives to the user a lot of information concerning the consumption, the execution time and the memory conflicts of his application. Enrico Macii: POET – Power Optimization for Embedded systems
Politecnico di Milano: POET is an energy consumption estimation and optimization flow for embedded system software. It is able to determine the energy consumption of a given project written in C. It internally relies on three estimation flows: an assembly-level estimation flow, a source-level estimation and optimization flow, and a library estimation flow.
Enrico Macci: CooLCD – Methods and tools for synthesizing energy-efficient LCD bus interfaces
Politecnico di Torino: CooLCD is a tool that allows to achieve energy-efficient transmission of graphical data over digital LCD interfaces by means of proper pixel-level encoding and direct RGB color approximation.

12.00 – 14.00: Mixed-Signal design and verification
Kaiping Zeng: RAMS – Refactoring for VHDL-AMS
Darmstadt University of Technology: The proposed code refactoring methodology restructures, refines, and simplifies an analog behavioural model written in VHDL-AMS by performing code transformations on the given model. Through code refactoring one improves the comprehensibility, expandability and reusability of the behavioural model and brings the model to a necessary preliminary stage for the actual circuit synthesis. The methodology has been implemented as a tool, which supports the top-down hierarchical design flow for analog and mixed-signal application and is part of the SAMS project.
Bernard Mourrain: Synaps – New approaches for solving polynomial equations
SINTEF ICT: Solving polynomial equations is needed in many areas, e.g. robotics, computer vision, computer aided design, and circuit validation & verification. The synaps library combining new numeric and symbolic techniques will be demonstrated.
Daniel Müller: Analog Performance Explorer
Technische Universität München: The Analog Performance Explorer is a tool that calculates a high-dimensional polytopal estimation of the feasible performance space of an analog circuit. Applications of the resulting estimates are in topology selection and hierarchical sizing of analog circuits.

14.00 – 16.00: Test tools
Maksim Jenihhin: Turbo Tester
Tallinn University of Technology: A freeware software package, running on different platforms will be presented that consists of the following test tools: test generation by different algorithms test set optimization, fault simulation for combinational and sequential circuits, testability analysis and fault diagnosis. It includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, BIST architecture simulators, design verification and design error diagnosis tools.
Christian Genz: SyCE – SystemC Environment
See description in “High level simulation, qualification and debug”

Descriptions

Short summaries of the software presentations (PDF documents, 10 - 1600 KB):
Description of ASIP
Description of BESST
Description of Diesel
Description of ESM
Description of gaut
Description of HSN
Description of IPWM
Description of METALL
Description of microprof
Description of nnse
Description of OSS
Description of PCC
Description of POET
Description of RAMS
Description of REDEFIS
Description of SC-VERIFIER
Description of SoftExplorer
Description of SUNMAP
Description of SYCE
Description of SymC
Description of SYMTA
Description of SYNAPS
Description of SYSTEMCASS
Description of TT
Description of TUDAPC
Description of xtractor