Suche

Lucas Klemmer, Johannes Kepler University Linz, AT Abstract We present a new verification approach for RISC-V processors which allows broadening existing test programs automatically. For a given test program our approach derives a second program that is different from the original one but proven to...

Markus Ulbricht, IHP, D Abstract To promote the advancement of RISC-V-processors into the safety-critical domain, we focus our investigations on reliability and resiliency. In this context, our main target is the development of a highly reliable pulpissimo-based multiprocessor platform with fault...

Sören Tempel, University of Bremen, D Abstract In this presentation we show an effective methodology for verification of RISC-V embedded software by integrating concolic testing with SystemC-based virtual prototypes. The integration involves extending the instruction set simulator to support...

Nehir Sonmez, Barcelona Supercomputing Center, ES Abstract eProcessor is a 3-year EuroHPC-JU project (started on April 2021) that involves 10 academic/industrial partners, which aims to provide an open source European RISC-V based out-of-order processor core, accelerators and a HW/SW stack, tailored...

Der edaWorkshop20 findet zusammen mit dem RISC-V-Activities-Workshop am 7. und 8. Oktober 2020 statt. Die gemeinsame virtuelle Veranstaltung startet mit dem edaWorkshop20 am 7. Oktober, der am 8. Oktober vormittags bis 11.00 Uhr fortgesetzt wird. Der RISC-V-Activities-Workshop startet am 8. Oktober...

Der edaWorkshop20 fand am 7. und 8. Oktober 2020 zusammen mit dem dritten RISC-V-Activities-Workshop ( Link) statt, wegen der bestehenden Reisebeschränkungen als reines Online-Event. Der Workshop bot auch im Jahr 2020 wieder ein hochinteressantes technisches Programm von insgesamt 10 Sessions (5...

Salaheddin Hetalani, Siemens EDA, DE Abstract RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to...

Eyck Jentzsch, MINRES Technolgies GmbH, DE Abstract RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to...

Der edaWorkshop20 fand am 7. und 8. Oktober 2020 zusammen mit dem dritten RISC-V-Activities-Workshop ( Link) statt, wegen der bestehenden Reisebeschränkungen als reines Online-Event. Der Workshop bot auch im Jahr 2020 wieder ein hochinteressantes technisches Programm von insgesamt 10 Sessions (5...

Larry Lapides, Imperas Software, US Abstract As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the...