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Uzair Sharif, Technical University of Munich, DE Abstract Fault tolerance against random hardware errors can be reached by software redundancy methods, which is also known as software-implemented hardware fault tolerance (SIHFT). As compiler optimization can remove this redundancy, SIHFT methods...

Ingo Feldner, Robert Bosch GmbH, DE Biography Ingo Feldner is a Project Lead for Virtual Hardware Platforms in the Central Corporate Research Division at Robert Bosch GmbH where he is dealing with the deployment of virtual platforms for productive use for different business units inside Bosch.Ingo...

Philipp Tomsich, Chair of the Software Horizontal Committe within RISC-V International, VRULL GmbH, AT Biography Dr. Philipp Tomsich is the Founder and Chief Technologist of VRULL GmbH, an engineering consultancy focused on engineering performance solutions through compiler optimizations, runtime...

Mark Himelstein, RISC-V International Biography Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing hardware and software product architecture, analysis, mentoring and interim management...

Drew Fustini, ambassador for RISC-V International, BayLibre, FR/USA Biography Drew Fustini is a Linux kernel developer at BayLibre and serves as an ambassador for RISC-V International. He sits on the board of directors for the BeagleBoard.org Foundation and the Open Source Hardware Association...

Der edaWorkshop21 findet als Verbund in digitaler Form zusammen mit dem RISC-V-Activities-Workshop vom 1.12.21 bis zum 2.12.2021 statt. zum edaWorkshop21-Programm zum RISC-V-Activities-Workshop-Programm

Die Stadt Hannover Hannover, Landeshauptstadt Niedersachsens, ist die Stadt im Grünen mit königlicher Geschichte und Veranstaltungsort der beiden größten Messen der Welt. Mit dem Flughafen Hannover und direkten Bahn- und Autobahnanbindungen ist Hannover im Zentrum Europas ideal erreichbar. Die...

Zhao Han, Infineon, D Abstract In order to enable efficient software and firmware development for a RISC-V core with custom instructions, full-featured SW debug capabilities are mandatory. This implies not only a customized hardware implementation of an on-chip debug system (OCDS), but also an...

Raphael Klink, University of Lübeck, D Abstract The sensors used in autonomous driving such as LiDAR, radar or camera are collecting huge amounts of data. Processing these amounts of data is costly, especially as reliability and power constraints are also important factors in autonomous driving. For...

Alexander Walsemann, University of Applied Sciences Dortmund, D Abstract The STRV is a RV32-IMC RISC-V core with integrated protection against Single-Event-Upsets (SEUs). It uses triple modular redundancy (TMR) and majority voting to automatically detect and correct encountered SEUs within the core...