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Drew Fustini, ambassador for RISC-V International, BayLibre, FR/USA Biography Drew Fustini is a Linux kernel developer at BayLibre and serves as an ambassador for RISC-V International. He sits on the board of directors for the BeagleBoard.org Foundation and the Open Source Hardware Association...

Der edaWorkshop21 findet als Verbund in digitaler Form zusammen mit dem RISC-V-Activities-Workshop vom 1.12.21 bis zum 2.12.2021 statt. zum edaWorkshop21-Programm zum RISC-V-Activities-Workshop-Programm

Die Stadt Hannover Hannover, Landeshauptstadt Niedersachsens, ist die Stadt im Grünen mit königlicher Geschichte und Veranstaltungsort der beiden größten Messen der Welt. Mit dem Flughafen Hannover und direkten Bahn- und Autobahnanbindungen ist Hannover im Zentrum Europas ideal erreichbar. Die...

Zhao Han, Infineon, D Abstract In order to enable efficient software and firmware development for a RISC-V core with custom instructions, full-featured SW debug capabilities are mandatory. This implies not only a customized hardware implementation of an on-chip debug system (OCDS), but also an...

Raphael Klink, University of Lübeck, D Abstract The sensors used in autonomous driving such as LiDAR, radar or camera are collecting huge amounts of data. Processing these amounts of data is costly, especially as reliability and power constraints are also important factors in autonomous driving. For...

Alexander Walsemann, University of Applied Sciences Dortmund, D Abstract The STRV is a RV32-IMC RISC-V core with integrated protection against Single-Event-Upsets (SEUs). It uses triple modular redundancy (TMR) and majority voting to automatically detect and correct encountered SEUs within the core...

Lucas Klemmer, Johannes Kepler University Linz, AT Abstract We present a new verification approach for RISC-V processors which allows broadening existing test programs automatically. For a given test program our approach derives a second program that is different from the original one but proven to...

Markus Ulbricht, IHP, D Abstract To promote the advancement of RISC-V-processors into the safety-critical domain, we focus our investigations on reliability and resiliency. In this context, our main target is the development of a highly reliable pulpissimo-based multiprocessor platform with fault...

Sören Tempel, University of Bremen, D Abstract In this presentation we show an effective methodology for verification of RISC-V embedded software by integrating concolic testing with SystemC-based virtual prototypes. The integration involves extending the instruction set simulator to support...

Nehir Sonmez, Barcelona Supercomputing Center, ES Abstract eProcessor is a 3-year EuroHPC-JU project (started on April 2021) that involves 10 academic/industrial partners, which aims to provide an open source European RISC-V based out-of-order processor core, accelerators and a HW/SW stack, tailored...