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Der edaWorkshop20 findet zusammen mit dem RISC-V-Activities-Workshop am 7. und 8. Oktober 2020 statt. Die gemeinsame virtuelle Veranstaltung startet mit dem edaWorkshop20 am 7. Oktober, der am 8. Oktober vormittags bis 11.00 Uhr fortgesetzt wird. Der RISC-V-Activities-Workshop startet am 8. Oktober...

Salaheddin Hetalani, Siemens EDA, DE Abstract RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to...

Eyck Jentzsch, MINRES Technolgies GmbH, DE Abstract RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to...

Der edaWorkshop20 fand am 7. und 8. Oktober 2020 zusammen mit dem dritten RISC-V-Activities-Workshop ( Link) statt, wegen der bestehenden Reisebeschränkungen als reines Online-Event. Der Workshop bot auch im Jahr 2020 wieder ein hochinteressantes technisches Programm von insgesamt 10 Sessions (5...

Larry Lapides, Imperas Software, US Abstract As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the...

Zdenek Prikryl, codasip, CZ Abstract On-chip processors have been traditionally grouped into silos like MCU, DSP, GPU and application processor. Designers have relied on Moore’s law rather than special architectural changes to achieve performance improvements. With gains from Moore’s law becoming...

Stefan Wallentowitz, Munich University of Applied Sciences, DE Abstract RISC-V is the perfect platform for teaching computer system fundamentals and computer architecture. It has an open and vivid ecosystem of tools and materials. This presentation gives a brief overview of RISC-V in education and...

Juan Camilo Santana Miranda, Fraunhofer IIS, DE Abstract This work in progress presents a SystemC-RTL implementation of a RISC-V core based on the PULP RISCY microarchitecture. We were aiming at a simple RISC-V core model that is easily expandable for complex models in software simulation and...

Wolfgang Ecker, Scale4Edge Project Coordinator, Infineon Technologies, DE Abstract RISC-V reached its 10th anniversary this May. It evolved in this decade as a de-facto standard ISA, being widely supported by universities, the open source community, and companies. The ISA is key for compiler support...

Paul Palomero Bernardo, University of Tuebingen, DE Paul Palomero Bernardo, Adrian Frischknecht, Dustin Peterson, University of Tuebingen, DE Abstract In this talk, we will present a configurable, low-power edge computing platform for efficient sensor signal processing. The platform is composed of a...