3rd European RISC-V Firmware and Embedded RUST Workshop 2025 Programm

Ares Tahiraga, Yash Rajan, Sinha Paritosh Kumar, Raphael Kunz, Stephanie Ecker, Sebastian Prebeck, Wolfgang Ecker, Infineon Technologies AG, DE

Topic: Hardware Abstraction Layer Topics

Abstract: RISCV CPU near peripherals are programmed either via CSRs or memory mapped registers. In some cases a mix of both options is allowed. Proven technologies for SW-interaction with HW-peripherals are software accessible registers also known as memory mapped registers. This proven technology cannot be applied when CSRs come into the play as different assembler instructions with different features are required for reading and writing the different accessible registers. The presentation shortly introduces code for memory mapped registers and discusses two alternatives to make peripheral access via CSRs in both cases to look like the same: CSR index-instructions or making all relevant CSRs SW accessible.

Projects: ISOLDE project (European, Chips JU (EU+National))

Luis Costero, Complutense University of Madrid, ES

Topic: Deployment for Extreme Edge AI

Abstract: The evolution from the so-called edge-to-cloud continuum to integrate low-power and embedded devices, driving it towards a sensor-to-cloud continuum, carries out important challenges. Among them, code and performance portability across layers in the continuum are two of the main concerns to integrate embedded devices into classical workload orchestrators. In this talk, we will evaluate the potential of Webassembly (WASM) as a feasible solution for the integration of this type of hardware within heterogeneous compute deployments including embedded devices. WASM promises transparent code portability, but performance portability is still an open question. For the specific case of RISC-V architectures across the continuum, and using Embench as a representative set of benchmarks, we will evaluate and compare the performance observed for interpreted WASM, AOT-compiled WASM and native executions, delving into performance details and discussing the pros and cons of the language in the context of a future sensor-to-cloud continuum.

Projects: Digital Autonomy with RISC-V in Europe (DARE), Spanish Open Hardware Alliance (SOHA)

Heidi Holappa, University of Helsinki, FI
Johannes Geier, Technical University of Munich, DE 

Topic: TRISTAN, RISC-V, Instruction Set Simulation, Testing, Debuggers

Abstract: We present a multi-ISA framework for verifying the correctness of Instruction Set Architectures (ISAs), their simulators, and compilers.
Our approach leverages DWARF debugging information to map common code base binaries compiled for different target architectures or with different compilation flows. This enables fine-grained simulation-based comparison of functional behavior across different target and compiler instances. 
A key contribution of our framework is the practical demonstration that the DWARF-based approach is both reusable and effective in various verification settings. We highlight its applicability, identify its limitations, and provide new insights into its constraints by demonstration in an RISC-V development context. While the current focus is on ISS vs. ISS comparison, the methodology also covers host-based execution by using its results directly as a golden reference for the ISS evaluation.

Projects: TRISTAN project (European, Chips JU (EU+National))

Philipp van Kempen, Technical University of Munich, DE
Co-presenter: Eyck-Alexander Jentzsch, MINRES Technologies GmbH, DE

Topic: Virtual Prototyping, Profiling, Static/Dynamic Analysis

Abstract: This presentation introduces a Python-based framework for trace-based performance profiling of RISC-V applications. Unlike traditional sample-based profilers, trace-based approaches provide fine-grained insights into program behavior, enabling precise identification of performance bottlenecks. We address the challenges of unifying diverse ISS trace formats, leveraging debug information to reconstruct call stacks, and accurately aggregating execution costs. The talk will also cover trace compression, scalability, and ongoing work, and will conclude with a short live demo utilizing multiple profiling backends.

Projects: Scale4Edge project (German, BMBF (National))

Conrad Foik, Technical University of Munich, DE

Topic: Virtual Prototyping

Abstract: When designing efficient embedded systems, performance is a key parameter that needs to be considered during both the software implementation and the validation of suitable hardware architectures. In the absence of actual hardware prototypes, so-called performance simulators are frequently used to evaluate the performance early on in the design process. 
The ETISS performance simulator is a simulation environment that combines highly accurate performance estimates with high simulation speeds. It also provides a tool flow for automatic adaptation to new processor variants based on compact microarchitecture descriptions, which is essential for an efficient design space exploration. Furthermore, the simulator estimates the performance on an instruction-by-instruction basis and is thus well suited for software profiling.
In this talk, we will give an overview of the ETISS performance simulator and then focus on a new tool for post-simulation analysis. This analyzer combines static code analysis with the performance estimates of the ETISS simulation and can therefore provide key metrics and visualizations, like the visualization of the processor's pipeline flow, mapped to specific functions of the target software.

Projects: GenerIoT project (European, ITEA (EU+National))

Henri Lunnikivi, Tampere University, FI

Topic: Real-time interrupt driven concurrency in Rust with some hardware acceleration

Abstract: Hard real-time systems need hardware and software to coordinate well for maximum performance. Through clever use of Rust language features, RTIC offers a highly programmable, sleek API with plenty of useful guarantees that also keep the firmware optimal performance-wise, while enabling the programmer to focus on the business function of each task.

We have refactored the traditional RTIC architecture to meet the scalability requirements of the relatively diverse RISC-V hardware ecosystem. As a bonus, we have obtained the ability to create both application- and hardware-specific DSL extensions and analysis passes in a highly modular way, and the ability to build streamlined multicore distributions of RTIC.

In this talk, I will explore the story of how the diversity of the RISC-V ecosystem clued us in on how to solve many architectural problems with a single stroke.

Projects: TRISTAN project (European, Chips JU (EU+National))

Julian Ganz, FZI Forschungszentrum Informatik, DE

Topic: Debugging and tracing

Abstract: The Efficient Trace for RISC-V, also known as ETrace, defines a RISC-V specific tracing format and algorithm for both instruction- and data-traces. We present riscv-etrace, an open source Rust library for processing and generating such traces suitable for a wide variety of encoder parameter sets and use-cases, including `nostd` contexts.
The talk briefly introduces core concepts of the instruction trace format and algorithm, highlighting key features of the protocol. After a short dive in an existing reference implementation we then present our Rust library. We show off its modular design and its adaptability to diverse use-cases. We conclude with a few example applications that make use of the library.

Projects: Scale4Edge project (German, BMBF (National))

Andreas Wallner, Infineon Technologies Austria AG, Graz, AT

Topic: Test, Safety

Abstract: We present our idea for flexible register access, complete with support for unittesting. We embrace the inherently unsafe nature of accessing hardware with side-effects. Enabling host-unittests for register-accessing code allows us to know that our drivers are correct and safe.

The lowest layer of all embedded firmware is interfacing to the hardware via writing memory-mapped registers. In Rust we have ways to provide usable and safer interfaces which remove many of the error sources we encounter when using C. Examples are the APIs generated by `svd2rust` or `chiptool`.

At Infineon, we want to make our Aurix controller family - among others - available to the Rust community. With our partners we chose to implement an alternative register interface, because

• due to the nature of many hardware modules, ownership semantics of Rust do not work well for the register level, and we think safety should be enforced at the driver layer
• register access must be extendable for niche use-cases like HW with intrinsic read-modify-write support or registers with page select
• a generated crate for registers should not have any dependencies or macros
• unittesting of register accessing firmware should be possible on a PC.

This alternative is `svd2pac` which we recently open-sourced - a generator that builds crates for register access given an industry standard SVD file.

As part of this alternative interface we also want to present `regmock-rs` - a testing framework that allows the user to test code that does register access. Embedded code can be run and be debugged on a normal developer machine.

Different levels of testing can be applied, from simply checking that registers are set to a given value, verifying that the order of operations is correct, up to running the code against a model of the hardware. Apart from fast development cycles, being on the host also allows us to inject simulated hardware errors.

Regmock completes our story as it allows us to achieve test coverage for low-level code can be both: useful and simple to write. Depending on the logic we are testing we can choose how to represent or simulate our hardware. Since our register accessing code is testable we can often flatten our architecture since we don't need logic-less layers that abstract hardware for the sole purpose of testing.

Horst Kargl und Rene Windegger, SparxSystems Software GmbH, AT

Topic: TBD

Abstract: Failed three times, rethought three times - and finally found a way. This session highlights the technical journey from model-based development to code generation for embedded devices with Rust on RISC-V. The often-heard phrase ""UML and Rust? That's not technically possible!"" was something we also had to deal with for a long time. And yes, it was frustrating: the usual tools fail, the target platform is demanding, and Rust doesn't want to be forced.
But: if you stop getting caught up in tool thinking and instead think about architecture, language properties and modelling methods together, new paths emerge. In this session, we will show how we rethought, what we failed at and what ultimately works - from model structure to target-specific templates, from ownership handling to integration with real toolchains.
No buzzwords. No marketing. Just real technology. For anyone who wants to know how model-based development with Rust for embedded systems can work after all.

Projects: GenerIoT project (European, ITEA (EU+National))

Raphael Kunz, Infineon Technologies AG, DE

Topic: Generation of a Runtime System using Generated Firmware for running Applications

Abstract: As the backbone of embedded systems, runtime systems play a central role in ensuring the reliability, performance, and efficiency of modern devices. However, manual implementation of runtime systems is a complex task. This presentation highlights a novel concept to automating runtime system generation for single-core processors using a Model-Driven Architecture approach. Our approach enables the automatic generation of runtime implementations in both C and Rust, ensuring a wide platform support and reducing development effort. By automating runtime system generation, we aim to simplify the development of embedded systems and improve overall efficiency.

Projects: TRISTAN project (European, Chips JU (EU+National))

Pawel Dzialo, Luleå University of Technology, SE

Topic: Firmware Verification

Abstract: Determining the correctness and timing characteristics of an embedded system is key to achieving safety and robustness.
In this presentation, we show how symbolic execution can be applied to automatically derive and prove these properties for an application, on the binary level, using the tool Symex. Furthermore, we show how the guarantees provided by Symex can be combined with the formal model underpinning RTIC to provide further guarantees regarding task isolation, schedulability and overall functional correctness.
The presented method can be applied almost entirely at compile time, and as such introduces no run-time overhead aside from initialization code on the order of 100 instructions. Future work includes more precise modeling of the underlying hardware, allowing tighter worst-case execution time bounding, and proving the equivalence between instruction set architecture(ISA) golden models and Symex ISA models.

Projects: RUST community

Malte Munch, Luleå University of Technology, SE

Topic: Software certification

Abstract:

• Certification is a relevant topic for many embedded applications.
• Frameworks exist to aid certification for software written in C such as MISRA C
• MISRA C consists of a set of rules that address issues caused by C not defining behaviour in all cases
• To which extent does Rust provide safety enhancements that are gained by applying MISRA C rules to C code?
• If Rust does mimic the guarantees that MISRA C gives, to which extent does that help in certification?

Projects: RUST community

Stephanie Ecker, Infineon Technologies AG | Chipglobe, DE

Topic: Driver generation

Abstract: Embedded firmware development often struggles with transitioning from high-level design to language-specific implementation, a potentially time-consuming and error-prone process. This presentation explores using the Model-Driven Architecture (MDA) approach to address this challenge by generating firmware driver code directly from abstract models.
Building on prior work that generated C code from these models, we are now extending this approach to include Rust. The ultimate vision is to demonstrate how the MDA methodology enables generation of idiomatic code for multiple languages while remaining implementation-agnostic.

Projects: TRISTAN project (European, Chips JU (EU+National))

Tiago Carvalho, ISEP & INESC-TEC, PT

Topic: RISC-V performance analysis, Real-time parallel Programming in RUST

Abstract: This presentation will provide insights on work being developed in two different areas:

• Lightweight Performance Monitoring of Real-Time Applications in RISC-V Platforms
• A Real-Time Parallel Programming Approach for Rust

Projects: GenerIoT project (European, ITEA (EU+National))