3rd European RISC-V Firmware and Embedded RUST Workshop 2025

Scope

Several European and national projects have work packages that address various aspects of firmware (hardware near software) for RISC-V and using RUST as an Embedded programming language. They include C/RUST firmware generation, C/RUST libraries, and validation as well as addressing various RISC-V ISAs including special instructions and closely/loosely coupled accelerators. They also include mechanisms supporting making firmware including virtual prototypes and debug to name only some. Also, several of the projects strive for making their software public available via various channels of open source.

Objectives

The objectives of the workshop are:

• Present advances as well as ongoing and planned activities in the scope of firmware development for RISC-V as well as using RUST as an embedded programming language.
• Discuss the taken strategies and implementation paths.
• Identify and align on joint technical activities to increase synergies.
• Jointly report the results in workshops, technical papers, special journal sessions or even books.

Workshop language: English

Venue

The two-day workshop will take place at the TU Wien on 18 and 19 Sept. Details on room and schedule (depending on the number of submissions) will be announced in early July.

Contributions and Registration

All researchers and engineers that work on RUST embedded programming and firmware development for RISC-V, especially all partners of the projects listed below, are kindly invited to present the current status of their work.

For registration, a title (until 12 June 2025) and an abstract (until 19 June 2025) of a talk/discussion contribution are wanted.

Title and abstract have to be registered at https://www.edacentrum.de/en/rvf/submission.

The costs for rooms, catering, dinners and social events will be distributed among the attendees. Attendance registration and free of charge cancellation can be done until 1 September 2025 AoE (= Anywhere on Earth) at a web page (to be communicated). Further information will be available in due time.

Relevant Project Tasks

GenerIoT (European, ITEA (EU+National))

• Task 2.2,2.3: (Meta)Models and Tools for making (Meta)Models
• Tasks 3.1, 3.2, 3.3: FW Generation and Virtual Prototyping (for Firmware Verification)

TRISTAN (European, KDT (EU+National))

• Task 4.4: Middleware (HAL) and Libraries (AI; DSP, BLAS, ...), C/C++ and RUST, Tools for generation …,
• Task 5.1: Virtual Prototype
• Task 5.3: Tools and methods for HW/SW system-level design and verification

ISOLDE (European, KDT (EU+National))

• Task 2.4: Software interfaces to general purpose cores
• Task 4.1, 4.2, 4.3: Libraries (Drivers), Tools for …

Scale4Edge (German, BMBF (National))

• Task 3.7: (Firmware for) Deployment for Extreme Edge AI
• Task 3.1, 3.8: DBT-RISE ETISS VP for FW verification

SoC HUB (Finnish, Business Finland (National))

• WP4 SW components Rust-based runtime for portable firmware across SoC Hub SoCs ▪ Used for bootloaders, validation tests and verification tests
• Automatic structural verification of IP-XACT based memory map metadata
• Priority-queue based hardware acceleration of a real-time OS (RTIC)
• OpenASIP programming paradigm for parallel computing

Organising and Technical Programme Committee

• Wolfgang Ecker, Infineon Technologies, DE
• Daniel Müller-Gritschneder, TU Wien, AT
• Timo Hämäläinen, Tampere University, FI
• Suvi Lammi, Tampere University, FI
• Henri Lunnikivi, Tampere University, FI
• Peter Lieber, SparxSystems Software GmbH, AT
• Max Höfferer, VÖSI, AT
• Ulf Schlichtmann, Technical University Munich, DE
• Johannes Geier, Technical University Munich, DE
• Andreas Vörg, edacentrum, DE