4th European RISC-V Firmware and Embedded RUST Workshop 2026

Scope

Several European and national projects have work packages that address various aspects of firmware (hardware near software) for RISC-V and using C/C++/RUST as an Embedded programming language. They include C/C++/RUST firmware generation, C/C++/RUST libraries, and validation as well as addressing various RISC-V ISAs including special instructions and closely/loosely coupled accelerators. They also include mechanisms supporting making firmware including virtual prototypes and debug to name only some. Also, several of the projects strive for making their software public available via various channels of open source.

Objectives

The objectives of the workshop are:

• Present advances as well as ongoing and planned activities in the scope of firmware development for RISC-V as well as using C/C++/RUST as an embedded programming language.
• Discuss the taken strategies and implementation paths.
• Identify and align on joint technical activities to increase synergies.
• Jointly report the results in workshops, technical papers, special journal sessions or even books.

Workshop language: English

Venue

Co-located with IEEE NorCAS 2026 (20–21 October 2026), Tampere University, Finland. The workshop takes place at the Tampere University city campus main building, across the street from the NorCAS venue (Tampere Hall).

Contributions and Registration

All researchers and engineers that work on C/C++/RUST embedded programming and firmware development for RISC-V, especially all partners of the projects listed below, are kindly invited to present the current status of their work.

For registration an abstract (until 31 August 2026) of a talk/discussion contribution is wanted.

Submit your abstract via the NorCAS conference submission system at conftool.pro/norcas2026, selecting as the target track: “4th European RISC-V Firmware and Embedded RUST Workshop”.

Attendee Registration

To register for the workshop, you can either add the workshop to your NorCAS registration, or register for the workshop only. The fee is 100 EUR (IEEE members) or 150 EUR (regular). Register at lyyti.fi/reg/norcas2026/en.
If you also plan to attend the full NorCAS conference (20–21 October), the same registration page lets you combine both.

Deadlines

Relevant Project Tasks

GenerIoT (European, ITEA (EU+National))

• Task 2.2,2.3: (Meta)Models and Tools for making (Meta)Models
• Tasks 3.1, 3.2, 3.3: FW Generation and Virtual Prototyping (for Firmware Verification)

TRISTAN (European, KDT (EU+National))

• Task 4.4: Middleware (HAL) and Libraries (AI; DSP, BLAS, ...), C/C++/RUST, Tools for generation …,
• Task 5.1: Virtual Prototype
• Task 5.3: Tools and methods for HW/SW system-level design and verification

ISOLDE (European, KDT (EU+National))

• Task 2.4: Software interfaces to general purpose cores
• Task 4.1, 4.2, 4.3: Libraries (Drivers), Tools for …

Scale4Edge (German, BMBF (National))

• Task 3.7: (Firmware for) Deployment for Extreme Edge AI
• Task 3.1, 3.8: DBT-RISE ETISS VP for FW verification

SoC HUB (Finnish, Business Finland (National))

• WP4 SW components RUST-based runtime for portable firmware across SoC Hub SoCs ▪ Used for bootloaders, validation tests and verification tests
• Automatic structural verification of IP-XACT based memory map metadata
• Priority-queue based hardware acceleration of a real-time OS (RTIC)
• OpenASIP programming paradigm for parallel computing

Organising and Technical Programme Committee

• Henri Lunnikivi, Tampere University (FI)
• Raphael Kunz, Infineon Technologies AG / TU Munich (DE)
• Per Lindgren, Luleå University of Technology (SE)
• Pawel Dzialo, Luleå University of Technology (SE)
• Malte Munch, Luleå University of Technology (SE)
• Andreas Vörg, edacentrum (DE)