RVF (RISC-V FW) - Workshop

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Attendee Registration

To cover the costs of the social events a cost-covering allocation to all participants will be done. With the attendee registration special diets can be communicated to the organisers.


Monday 2 October

Morning 9 – 11

Peter Lieber: State of Art Model Based Software Engineering with Focus on Variant/Version Management and Code Generation Capabilities

Henri Lunnikivi: Role of software in a large SoC design project: case SoC Hub Headsail

Lunch break 11.15 – 12.30

Afternoon 12.30 – 17

Wolfgang Ecker: Device Driver Auto-Generation - Status and Challenges

Mayuri Bhadra: An MDA based Approach for Target Language Independent Sequential Code Generation

Tobias Müller: Firmware Development Support for AI acceleration with the Rocket Chip design flow

Per Lindgren: Beyond Rust Memory Safety

Dinner 19 ->

Tuesday 3 October

Morning 8 – 12

Rocco Jonack: Early FW validation and performance estimation using DBT-RISE and open-source based TLM2 models

Conrad Foik: ETISS: A Flexible and Extendable Simulator for FW-Development

Pawel Dzialo: SyncRim for HW/SW Modelling and Simulation

Rotar Danut: You Synthesize what you simulate

Lunch break 12 – 14

Afternoon 14 – 18

Philipp van Kempen: muRISCV-NN: Deep-Learning Inference Kernels for Embedded Platforms using the RISC-V Vector and Packed Extensions

Kari Hepola: OpenASIP

Aisha Ahmed: Rust on PULP-platform processors (Ibex, RI5CY): runtime and interrupts

Andrew Wilson: Exploring Approaches to RISC-V Hardware Acceleration at the Firmware and Software Level

Dinner 19 ->

Wednesday 4 October

Morning session and discussions 9 – 12, TBD


Several European and national projects have work packages that address various aspects of firmware (hardware near software) for RISC-V. They include firmware generation, libraries, and validation as well as addressing various RISC-V ISAs including special instructions and closely/loosely coupled accelerators. They also include mechanisms supporting making firmware including virtual prototypes and debug to name only some. Also, several of the projects strive for making their software public available via various channels of open source.


The objectives of the workshop are:

  • Present the ongoing and planned activities in the scope of firmware development for RISC-V.
  • Discuss the taken strategies and implementation paths.
  • Identify and align on joint technical activities to increase synergies.
  • Jointly report the results in workshops, technical papers, special journal sessions or even books.


  • Oct 2: Room Paidia in the Nokia Arena (Kansikatu 3, 33100 Tampere, Finland; in Google Maps)
  • Oct 3+4: Building Lyhty at the Tampere University campus; in Google Maps

Workshop language: English

Contributions and Registration

All researchers and engineers that work on firmware development for RISC-V, especially all partners of the projects listed below, are kindly invited to present the current status of their work.

For registration, a title (until 1 September 2023 15 September 2023) and an abstract (until 15 September 2023) of a talk/discussion contribution are wanted.

Title and abstract have to be registered at https://www.edacentrum.de/en/rvf/submission.

The costs for dinners and social events will be distributed among the attendees. Attendance registration and free of charge cancellation can be done until 22 September 2023 AoE (= Anywhere on Earth) at a web page (to be communicated). Further information will be available in due time.

Relevant Project Tasks

GenerIoT (European, ITEA (EU+National))

  • Task 2.2,2.3: (Meta)Models and Tools for making (Meta)Models
  • Tasks 3.1, 3.2, 3.3: FW Generation and Virtual Prototyping (for Firmware Verification)

TRISTAN (European, KDT (EU+National))

  • Task 4.4: Middleware (HAL) and Libraries (AI; DSP, BLAS, ...), C/C++ and RUST, Tools for generation …,
  • Task 5.1: Virtual Prototype
  • Task 5.3: Tools and methods for HW/SW system-level design and verification

ISOLDE (European, KDT (EU+National))

  • Task 2.4: Software interfaces to general purpose cores
  • Task 4.1, 4.2, 4.3: Libraries (Drivers), Tools for …

Scale4Edge (German, BMBF (National))

  • Task 3.7: (Firmware for) Deployment for Extreme Edge AI
  • Task 3.1, 3.8: DBT-RISE ETISS VP for FW verification

SoC HUB (Finnish, Business Finland (National))

  • WP4 SW components
    • Rust-based runtime for portable firmware across SoC Hub SoCs
      • Used for bootloaders, validation tests and verification tests
    • Automatic structural verification of IP-XACT based memory map metadata
    • Priority-queue based hardware acceleration of a real-time OS (RTIC)
    • OpenASIP programming paradigm for parallel computing


Title registration extended deadline:

Sep 1, 2023 AoE*)
Sep 15, 2023 AoE*)

Short abstract deadline:

Sep 15, 2023 AoE*)

Author notification:

Sep 22, 2023 AoE*)

Program available:

Sep 25, 2023 AoE*)

Attendee registration deadline:

Sep 22, 2023 AoE*)
Sep 27, 2023 AoE*)

*) AoE = Anywhere on Earth

Organising Committee

  • Wolfgang Ecker, Infineon Technologies, DE
  • Timo Hämäläinen, Tampere University, FI
  • Suvi Lammi, Tampere University, FI
  • Henri Lunnikivi, Tampere University, FI
  • Andreas Vörg, edacentrum, DE

In case of questions, please contact Andreas Vörg voergatedacentrum [dot] de.