Slashing R&D Waste - Best Practices in IC Lifecycle Management, from Concept to Volume Production

DruckversionPer E-Mail sendenPDF-Version

Ronald Collett,President and CEO, of Numetrics Management Systems, Inc.


Each year semiconductor and electronics companies collectively spend billions of dollars on chip development projects that end up getting cancelled. For the most part, the R&D is wasted, because only a fraction of the scrap typically can be leveraged into other projects. It goes without saying that there’s an enormous and direct impact on each company’s financial bottom line. What’s more, these projects chew up precious resources that could be allocated to other projects, which themselves end up missing schedule because they’re inadequately staffed. Late market entry translates into billions of dollars in lost market share annually among competitors.

Indeed, the semiconductor industry misses its product development schedules 85 percent of the time, with the average overrun exceeding 50 percent of the originally planned cycle time. Much of this waste can be avoided by applying best practices at both the portfolio and project level, across the full IC development lifecycle—i.e. from project inception through release to volume production. But what are these portfolio and lifecycle management practices and how are they applied?

On the one hand, the practices seem obvious because it’s easy to understand why projects are cancelled and miss schedules so badly. It’s the “usual suspects,” such as instability of manufacturing process and libraries, EDA tool and methodology problems, ill-defined and continuously changing specifications, development team inexperience and/or lack of cohesiveness, IP whose delivery is delayed or doesn’t work as planned, unanticipated technical problems in hardware and/or software, and the premature departure of key resources from the project. Managers know these all too well. But the problem they face is the uncertainty regarding which ones will occur on any particular project and the specific impact of each on schedule. What’s missing is an easy, yet reliable, approach for accurately quantifying the aggregate risk associated with each project and an efficient process that effectively mitigates it.

In developing its unique solution, Numetrics benchmarked and studied over a thousand IC development projects from over 50 semiconductor and electronics companies. This talk delves into the rapidly emerging portfolio and lifecycle management practices that are positively impacting the financial bottom line of semiconductor companies and electronics companies involved in IC development.

Curriculum Vitae

Ronald Collett Ronald Collett has spent nearly 25 years in the electronics industry, where he has held positions in executive management, engineering, marketing and sales. He founded Collett International, Inc. in 1992, a research and consulting company specializing in design technology strategy for semiconductor and electronic design automation (EDA) companies. He also spent several years at the Dataquest division of the Gartner Group, a technology research and consulting firm, where he oversaw the firm’s activities in the areas EDA, application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).

He has published over 100 articles on the design of integrated circuits (ICs) and electronic systems in publications including Electronic Engineering Times, Nikkei Asia Electronics, Nikkei Electronics, Nikkei Micro Devices, Electronic System Design and, most recently, Fabless Forum.

Mr. Collett holds a Bachelor of Science degree in electrical engineering from Drexel University, a degree in law from Santa Clara University, and he is member of the California Bar.