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Termin Dienstag, 28. Oktober 2008 9:00h bis ca. 17:00h Wir starten den Workshop am Vorabend (Montag, 27.10.2008) um 19.00h mit einem ersten Gedankenaustausch im Restaurant Zwischenzeit. Tagungsort Werkhof Hannover Nordstadt Seminarraum 1 Schaufelder Str. 11 30167 Hannover http://www.werkhof-hannover...

"More Solutions Provided by EDA Vendors" In order to realize the fascinating applications and promising business opportunities discussed in edaForum08´s sessions it is indispensable to have access to professional tools and design flow solutions, completed by professional services. In an exhibition...

Technical Session 1 The Deep Submicron Hell of Physical Design Jacques Benkoski, President and CEOMonterey Design Systems, Inc. Abstract Design closure is commonly viewed as an activity that happens at the end of the design process. This leads to long, expensive iterations but more importantly...

Business Session 2 Seed, Care and Harvest - Value Focused EDA Keynote Jacques Benkoski, Vice ChairmanEDA Consortium Abstract Since the inception of Moore's Law in 1965, the pursuit of the latest and greatest semiconductor technology has been synonymous with growth, profitability, and market share...

Technical Session 1 The Deep Submicron Hell of Physical Design Markus Bühler, ASIC Design CenterIBM Microelectronics Abstract During the last years multi-million transistor ASICs with several millions instances have become common. Due to shrinking technology the silicon space on a chip enables more...

Technical Session 2 The 7th Heaven of System Level Design Mark Burton, Engineering Manager Arm Ltd. Abstract This talk will describe the Transaction Levels of modeling within SystemC. The various abstraction levels within Transaction Level Modeling (TLM) are identified, and the overview of the APIs...

Business Session 2 Seed, Care and Harvest - Value Focused EDA Abstract Andreas Demleitner, Senior Investment Manager Bay Tech Venture Capital Europe holds a strong position in EDA research, in particular in System-level and mixed signal EDA. National, European and industrially funded research at...

Technical Session 2 The 7th Heaven of System Level Design Peter Flake, ScientistSynopsys, Inc. Abstract There is a need to design and verify systems at an abstraction level which reflects some of the architecture and performance of the system under design, without too much detail. The communication...

Business Session 1 Measure or Die - Design Productivity Andrew B. Kahng, Professor at the Computer Science Department University of California, San Diego Abstract The 2001 International Technology Roadmap for Semiconductors introduced a new design cost model that highlighted both the cost of design...

Business Session 1 Measure or Die - Design Productivity Jürgen Koehl, Senior Technical Staff Member, ASIC Design Center IBM Microelectronics, Inc. Abstract A key factor in the time-to-market for an ASIC design is turnaround time (TAT). Because of the ever-increasing complexity of ASIC designs, a 30%...