Submission Page for the 4th Workshop on RISC-V Activities

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Workshop on RISC-V Activities Logo

This joint academic/industry workshop aims to stimulate the exchange of information among the attendees about already existing or planned RISC-V activities. The workshop provides a platform for how these activities can be extended across projects or to develop innovative ideas, activities, and collaborations. This workshop has been initiated by the BMBF funded projects SAFE4I and Scale4Edge and will be executed in conjunction with the edaWorkshop21.

Date: 2 December 2021 9:00-18:00 CET

Location: Online with Microsoft Teams

Workshop language: English

About the Workshop series:

We will have two invited keynote talks for the topic "Towards Trustworthy RISC-V Processors for Safety-critical Applications"

RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to configure and customize the RISC-V ISA in accordance to the system needs, including custom instructions, is one of its strongest appeals, making custom RISC-V CPUs an attractive choice for an unprecedented number of companies. However, the challenge of actually designing a RISC-V core with custom extensions and ensuring its correct functional behaviour is still significant, even more in environments with high safety and security expectations. In this session, we present an automated flow to generate RISC-V cores with custom extensions together with their complete verification.

Talk 1: Towards Trustworthy RISC-V Processors for Safety-critical Applications
Eyck Jentzsch (MINRES Technologies, D)Eyck Jentzsch (MINRES Technologies, D)
Biography: Eyck Jentzsch holds a Dipl.-Ing. from the Technical University Ilmenau and has more than 25 years experience in microelectronics and semiconductor design. He is working at MINRES as General Manager and focuses on virtual platform modelling, development, and application as well as RISC-V IP development and verification. Prior to that he worked at Cadence Design Systems Inc. And Siemens in various full- and semi-custom as well as system level design and verification positions.
Talk 2: Towards Trustworthy RISC-V Processors for Safety-critical Applications
Salaheddin Hetalani (Siemens EDA, D)Salaheddin Hetalani (Siemens EDA, D)
Biography: Salaheddin Hetalani holds a M. Sc. in Embedded Computing Systems as a joint degree from the Technical University of Kaiserslautern and Southampton University and has around 3-year experience in formal design verification. He is working at Siemens EDA as Field Application Engineer and focuses on application and development of RISC-V and bus protocol VIPs

And we will have a panel session with the confirmed panelists:

  • Mark Himelstein, CTO RISC-V International, CH
  • Philipp Tomisch, TU Vienna and VRULL GmbH, AT - Leader RISC-V Software Horizontal Committee
  • Further panelists will be announced



Short abstract deadline:

Oct 24, 2021 AoE*)

Author notification:

Nov 7, 2021 AoE*)

Program available:

Nov 11, 2021 AoE*)

Registration deadline:

Nov 25, 2021 AoE*)

*) AoE = Anywhere on Earth

Organizing Committee

  • Oliver Bringmann, Universität Tübingen, DE
  • Wolfgang Ecker, Infineon Technologies, DE
  • Andreas Mauderer, Robert Bosch GmbH, DE
  • Daniel Müller-Gritschneder, Technische Universität München, DE
  • Wolfgang Müller, Universität Paderborn, DE
  • Dieter Treytnar, edacentrum, DE
  • Andreas Vörg, edacentrum, DE
  • Stefan Wallentowitz, Hochschule München, DE

In case of questions, please contact:
Andreas Vörg or Dieter Treytnar
risc-vatedacentrum [dot] de

Submission Page

Submission page for the 4th Workshop on RISC-V Activitites
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