LLM-Assisted High-Level Synthesis and Testbench Generation for Digital Design

Abstract

With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more efforts in circuit design and verification. The workflow of digital design, however, often involves repeated modifications in many iterations, which are labor-intensive and error-prone. Therefore, there is an increasing need for more efficient and cost-effective Electronic Design Automation (EDA) solutions to accelerate hardware development. Recently, large language models (LLMs) have made significant advancements in contextual understanding, logical reasoning, and response generation. Since hardware descriptions and intermediate scripts can be expressed in text format, it is reasonable to explore whether integrating LLMs into EDA could simplify and automate the circuit design workflow. This talk discusses the application of LLMs in HLS (High-Level Synthesis) code repair and testbench generation as well as future challenges and opportunities.

Biography

Bing Li is currently a professor leading the Digital Integrated Systems Group at the University of Siegen. His research interests cover AI-assisted EDA, circuit and system architectures, and emerging technologies such as RRAM and optical accelerators for neural networks. He has served on the technical program committee of major conferences including DAC, ICCAD, DATE, ASP-DAC, etc., and as program chair of ACM/IEEE International Workshop on Machine Learning for CAD (MLCAD) in 2022 and 2023.