IBM ASIC Design TAT Reduction
Business Session 1
Measure or Die - Design Productivity
Jürgen Koehl, Senior Technical Staff Member, ASIC Design Center IBM Microelectronics, Inc.
Abstract
A key factor in the time-to-market for an ASIC design is turnaround time (TAT). Because of the ever-increasing complexity of ASIC designs, a 30% reduction in TAT simply keeps the development time at a constant level in the evolution from one technology node to the next. More time must be shaved from TAT to reduce the overall development time.
The base for this improvement was a detailed analysis of the major contributors to design TAT. The improvement presented in this talk, include algorithmic improvements, new sign off criteria, a higher degree of automation and more powerful IT equipment.
Putting all these measures in place, IBM has reduced the time required to process the production netlist by 60% in a two-year window. These TAT reductions and the higher complexity of the 130 nm technologies result in a triple productivity improvement from one technology node to the next.
It will be shown that the main contributors to design TAT changed as a result of this work. The placement and timing closure step with ideal clocks, that dominated the TAT in 2001 is by now no longer the bottleneck and the focus shifted to the percentage of TAT spent on post routing timing and noise closure. The improvements put in place to address this part of the process will be outlined.
Curriculum Vitae
Jürgen Koehl studied Mathematics in Bonn and Paris. Prior to joining the IBM development lab in IBM Boeblingen in 1989, he was a member of the VLSI research team at the Institute for Discrete Mathematics in Bonn, Germany. Together with IBM’s research partners in Bonn he implemented one of the first timing driven design systems which was used for the first IBM CMOS S/390 processors. From 2001 to 2003 Juergen Koehl was on assignment to Burlington, Vermont to lead the world wide ASIC design turn-around-time reduction for IBM’s ASIC Design centers. Currently he is a Senior Technical Staff Member in the IBM ASIC Design Center in Boeblingen, Germany.
