Design and Process Interactions at the 32nm Node and Virtual IDM Environment

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Simon Yang, Chartered Semiconductor Manufacturing


As we arrived at the physical limits of CMOS technology, conventional scaling methodology is no longer viable to maintain the technology progress on the traditional trend characterized by Moore’s Law. On the other hand, due to the proven SOC integration capability and the convergence of applications on hand-held platforms, the appetite of the market for more transistors in a chip, lower power consumption, and faster operation speed at lower cost is far from tamed. As a result, the need for innovation in the semiconductor industry intensified in recent years. High K metal gate materials, air-gap interconnects, and EUV lithography are the examples of the newest technologies in play which were not considered in the realm of reality just a few years ago.

It becomes more important and urgent than ever for product design members in fabless community to have intimate understandings of process technologies, even during the early stages of technology R&D. This is because that: (1) Most of the new technologies have not only strong interactions with design styles in the area of manufacturing robustness (the traditional issues covered by DFM) but also design restrictions/guidance for achieving the promised product performance gains; (2) It is necessary in order to compete with leading IDMs in term of Time-To-Market. For years, good IDM companies have practiced simultaneous technology development and product design through close communication among the groups and certain build-in elasticity in the infrastructure to achieve rapid volume ramp after the qualification of each new technology node. The foundry-fabless arrangement historically lags leading IDMs in this ramp by >2 years due to the sequential nature of process technology development, circuit IP design and verification, and product design and qualification. This situation was somewhat tolerable largely because they were playing in different application markets. The dynamics will certainly change when the applications start to converge onto a common platform. EDA industry is clearly positioned to play a vital role in addressing these opportunities during the exciting period.

In this talk, we will first report, from the view of semiconductor technology and manufacturing specialists, the current status of Moore’s Law and our pursuit for "More Moore" and "More Than Moore". The technology innovation and the resulting breakthroughs highlighted are targeted to underpin the joint development in New York among IBM, STM, Freescale, Infineon, Samsung, and Chartered and the design enablement and manufacturing infrastructure accessible to the fabless community through the Common Platform manufacturing and enablement alliance of Chartered, IBM, and Samsung. Special focus will be given to the recently announced breakthrough 32nm technology with the introduction of High K Dielectric and Metal Gate.

Specific examples (such as gate capacitance vs gate leakage and Vt variation vs transistor gate area) will be described to demonstrate the critical breakthrough of the “physics limits” under traditional scaling methodology. Since all of this technology prowess will be for naught if the entire design infrastructure and enablement eco-system is not brought to the same level of sophistication and capabilities, the business constructs of the entire ecosystem surrounding the technology will then be described, including a brief exploration of how this model has evolved over time. A brief description of some of those EDA systems attuned to the 32nm technology currently being deployed will also be given. Lastly, we will talk about the need for the so called virtual IDM collaborative work infrastructure among foundry, IP vendors, and fabless companies to improve time-tomarket at new technology introductions, together with some discussions on the possible methodologies to achieve that.

Curriculum Vitae

Herr Simon YangDr. Simon Yang joined Chartered in October 2005 where he is responsible for developing and driving strategic programs in support of Chartered’s corporate objectives and long-term strategic direction.

Dr. Yang brings more than 20 years of experience in the semiconductor industry. He previously held key positions in technology development and advanced fab operations. He was a senior vice president for logic technology development and manufacturing at Semiconductor Manufacturing International Corporation (SMIC) and prior to that, a director of logic device and process integration at Intel. Prior to joining Chartered, he was president and CEO of Ciwest, a semiconductor start-up based in China.

Dr. Yang has been awarded more than 12 U.S. patents and is the author or co-author of more than 30 technical papers. He holds a bachelor’s degree in electrical engineering from Shanghai University of Science and Technology, and a MS in physics and Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, New York.