1st International Workshop on RISC-V Research Activities - Program

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At this web page you find the programme of the 1st International Workshop on RISC-V Research Activities. You may expand the programme for each session by clicking on the session title. You will find the detailed timetable, presentation titles and author names. If additional information like an abstract, curriculum vitae or (for attendees of the 1st International Workshop on RISC-V Research Activities only) slides is available, a link below the presentation title is displayed.

Thursday, June 21, 2018

09:00 - 09:30
Session 0: Welcome & Introduction

09:30 - 12:00
Session 1: RISC-V Virtual Platforms

09:30Extendable Translating Instruction Set Simulator (ETISS) with RISC-V Support and SYstemC/TLM Pulpino Virtual Platform
09:45Extensible and Configurable RISC-V based Virtual Prototype
10:00MINRES Assets & Interests project ideas in the area of VP based design and development methods
Coffee Break
10:45Current and Future Activities for RISC-V Virtual Prototyping and Chip Design
11:00A context-sensitive PEG-based timing model for a PULPINO-derived RISC-V microprocessor

12:00 - 13:00
Lunch Break

13:00 - 15:30
Session 2: RISC-V-Hardware-Architecture and Extensions

13:00Design of an Ultra Low Power RISC-V Platform with On-Chip-Tracing in 22FDX
13:15Hardware/Software Co-Design with the Rocket-Chip Generator
13:30A Low-Latency Lean DDR3 Controller and PHY in 65nm for PULP(ino) based Systems
Coffee Break
14:15Analyzing OpenSource for Safety and Security Applications
14:30Automated Verification of RISC-V-conform Floating-Point Modules

14:00 - 14:15
Coffee Break

15:45 - 17:15
Session 3: Future Research

15:45Identification and discussion of research topics
16:45Wrap up