Publications

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  1. HNI Newsletter Ausgabe 01 2020 der Universität Paderborn „Neues Verbundprojekt Scale4Edge“. S.8: https://www.hni.uni-paderborn.de/fileadmin/Publikationen/hni_aktuell/hni_aktuell_1_2020.pdf
  2. Ecker: Pressekonferenz „Vertrauenswürdige Elektronik“ am 9.6.2020
  3. Pressemeldung der TU Kaiserslautern am 6.7.2020
  4. Ecker: Silicon Saxony: Vortrag am 11.9.2020
  5. Best Paper Award: "Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study", Vladimir Herdt, Daniel Große, Universität Bremen, DE, Eyck Jentzsch, MINRES Technologies GmbH, DE, Rolf Drechsler, Universität Bremen, DE, FDL 2020, September 2020
  6. Ecker: ZuSE Workshop am 22.9.2020
  7. Pressemitteilung IFX, am 24. September 2020 „Projekt Scale4Edge startet im Rahmen der Leitinitiative „Vertrauenswürdige Elektronik“ des Bundesforschungsministeriums - Skalierbares Ökosystem für Spezialprozessoren für das Internet der Dinge wird angestrebt“ (https://www.infineon.com/cms/de/about-infineon/press/press-releases/2020/INFXX202009-090.html)
  8. Pressemitteilung OSS mit TUK, RB und MNRS, im September 2020
  9. Von TUK wurden vier Vortragsbeiträge zum Intel internen SCAP Workshop 2020 (virtuell) eingeladen und geleistet, 28.9.-1.10.2020.
  10. Organisation RISC-V Workshop am 8.10.2020
  11. Keynote: Invited Talk: RISC-V Scale4Edge Ecosystem - Motivation and Objectives, Wolfgang Ecker (Infineon, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  12. A RISC-V based Edge Computing Platform with Interchangeable Cores Using 22FDX, Paul Palomero Bernardo, Adrian Frischknecht, Dustin Peterson, University of Tuebingen, D, Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  13. Energy Efficient RISC-V Implementations in 22 nm, Heiner Bauer (Technical University of Dresden, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  14. A Compiler Comparison in the RISC-V Ecosystem, Mehrdad Poorhosseini, Kim Grüttner, Wolfgang Nebel (OFFIS, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  15. Efficient RISC-V Processor Verification via Cross-Level Testing, Vladimir Herdt (University of Bremen / DFKI, D), Eyck Jentzsch (MINRES Technologies, D), Daniel Große (Johannes Kepler University Linz, AT), Rolf Drechsler (University of Bremen / DFKI, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  16. A Configurable Virtual Prototyping Environment for Different RISC-V ISA Subsets, Peer Adelt (University of Paderborn, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  17. Security Issues in Hardware/Firmware interaction – Can a formal analysis of (just) the hardware help?, Johannes Müller (Technical University of Kaiserslautern, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  18. Ecker: Vorstellung von Scale4Edge von auf der EFECS 2020, 25.-26.11.2020
  19. UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting by Paul Palomero Bernardo, Christoph Gerum, Adrian Frischknecht, Konstantin Lübeck, and Oliver Bringmann, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, Issue: 11, Nov. 2020, http://dx.doi.org/10.1109/TCAD.2020.3012320.
  20. RISC-V Summit 2020 with "Scale4Edge project introduction" by Wolfgang Ecker, Lead Principle Engineer, Infineon Technologies, Virtual Event, Tuesday, 8 December 2020 12:00pm - 12:20pm - PST (Pacific Standard Time, GMT-8); https://tmt.knect365.com/risc-v-summit/
  21. Kunz, M. Fadiheh: “A Formal RTL Verification Approach for Detecting Transient Execution Side Channels in Processors”, Intel – IPAS Tech Sharing Forum, Dezember, 2020
  22. Vortrag auf der Onespin User-Konferenz OSMOSIS 2020: W. Kunz: “Hardware Security Verification using Unique Program Execution Checking”, 1.-2.12.2020, (virtuell).
  23. GLSVLSI 2020: "Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes", UB
  24. ATVA 2020: "RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms", UB
  25. ICCD 2020: "Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime", UB
  26. Vladimir Herdt, Sören Tempel, Daniel Große, and Rolf Drechsler. Mutation-based Compliance Testing for RISC-V. In 26th Asia and South Pacific Design Automation Conference (ASPDAC ’21), January 18–21, 2021, Tokyo, Japan. ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3394885.3431584
  27. Vortrag und Panel Diskussion: Wolfgang Ecker “European collaboration: Scale4Edge project introduction”, SOC HUB LAUNCH – BOOST COMPETITIVENESS THROUGH SYSTEM-ON-CHIP at Tampere. Smart City Week, Online, 27.01.2021, https://smarttampere.fi/en/home/
  28. An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes, Sören Tempel1 Vladimir Herdt1;2 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, DATE 2021
  29. Extending Verilator to enable Fault simulation, Endri Kaja1,2, Nicolas Ojeda Leon1,4, Michael Werner1,3, Bogdan Andrei-Tabacaru1, Keerthikumara Devarajegowda1, Wolfgang Ecker1,3, 1Infineon Technologies AG, Germany, 2Technische Universität Kaiserslautern, Germany, 3Technische Universität München, Germany, 4Darmstadt University of Applied Sciences, Germany, MBMV, Virtuell, 18.-19.3.2021.
  30. On Self-Verifying DSL Generation for Embedded Systems Automation, Zhao Han1,2, Shahzaib Qazi2, Michael Werner1,2, Keerthikumara Devarajegowda1,3, Wolfgang Ecker1,2, Infineon Technologies AG1 - Technical University Munich2 - Technical University Kaiserslautern3, MBMV, Virtuell, 18.-19.3.2021.
  31. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules, Peer Adelt, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, Heinz Nixdorf Institut/Universität Paderborn, Paderborn, Germany, MBMV, Virtuell, 18.-19.3.2021.
  32. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion, Sallar Ahmadi-Pour1, Vladimir Herdt1;2, Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, MBMV, Virtuell, 18.-19.3.2021.
  33. Towards RISC-V CSR Compliance Testing, Niklas Bruns, Vladimir Herdt, Daniel Große, Senior Member, IEEE and Rolf Drechsler, Fellow, IEEE; IEEE EMBEDDED SYSTEMS LETTERS (ESL) journal, VOL. 13, NO. 1, MARCH 2021
  34. Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing, UB, DAC 2021, December 5-9, 2021, virtual
  35. FZI plant ein Arbeitsergebnis aus Scale4Edge auf dem MBMV-Workshop im Rahmen einer live Demonstration, am 19.03.2021, zu präsentieren. Für die Veröffentlichung und zur besseren Einsichtnahme findet sich das Werkzeug auf GitHub: https://github.com/fzi-forschungszentrum-informatik/chips-core. Hierbei handelt es sich um die CHIPS (Chisel Hardware Property Specification) Sprache sowie unterstützendes Tooling.
  36. New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core, Nikolaos I. Deligiannis1, Riccardo Cantoro1, Matthias Sauer3, Bernd Becker2, Matteo Sonza Reorda1, 2 of Freiburg - Freiburg, Germany, 1Politecnico di Torino, DAUIN - Torino, Italy, 3Advantest - Böblingen, Germany, 26-28.4.2021, IEEE VTS 2021, Virtual
  37. μRV32: An Open Source RISC-V Cross-Level Platform for Education and Research, Sallar Ahmadi-Pour1, Vladimir Herdt1,2, Rolf Drechsler1,2, 1University of Bremen, 2DFKI GmbH Bremen, Germany, DESTION 2021, 18.5.2021.
  38. Krishnamurthy, Pradeep, & Poppen, Frank. (2021, May 17). Implementing VexRiscv Based Murax SoC on Arty A7 Artix-7 PCB from Digilent and Enabling JTAG Connection through Xilinx's BSCANE2 Debug IP. Zenodo. http://doi.org/10.5281/zenodo.4767195
  39. Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform, Vladimir Herdt1;2 Daniel Große2;3 Sören Tempel1 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, 3Institute for Complex Systems, Johannes Kepler University Linz, Austria in Journal of Systems Architecture (JSA), Elsvier, 2021
  40. Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V, Rafael Stahl, Technical University of Munich, RISC-V Forum on "Developer Tools & Tool Chains", 2.6.2021
  41. Johannes Müller, Mohammad R. Fadiheh, Anna Duque Anton, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz :“A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level”, IEEE/ACM Design Automation Conference (DAC), Dec. 5-9, 2021, San Francisco/virtual, USA. (accepted)
  42. RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems, UB, FDL 2021
  43. In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes, UB, FDL 2021
  44. Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level, Frank Riese1 Vladimir Herdt1;2 Daniel Große3 Rolf Drechsler1;2 1Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany 2Institute of Computer Science, University of Bremen, 28359 Bremen, Germany 3Institute for Complex Systems, Johannes Kepler University Linz, Austria Frank [dot] Rieseatdfki [dot] de, vherdtatuni-bremen [dot] de, daniel [dot] grosseatjku [dot] at, drechsleratuni-bremen [dot] de, UB, VLSI SoC 2021
  45. Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead, Oliver Bringmann1, Wolfgang Ecker2, Ingo Feldner3, Adrian Frischknecht1,Christoph Gerum1,Timo Hämäläinen4, Muhammad Abdullah Hanif5, Michael J. Klaiber3, Daniel Müller-Gritschneder6, Paul Palomero Bernardo1,Sebastian Prebeck2, Muhammad Shafique7; 1 University of Tübingen, 2 Infineon Technologies AG, 3 Bosch Corporate Research, 4 Tampere University, 5 Technische Universität Wien, 6 Technical University of Munich, 7 New York University Abu Dhabi, Special Session, ESWEEK 2021, Virtual Conference, October 10 – 15, 2021
  46. Advanced Virtual Prototyping for Cyber-Physical Systems using RISC-V: Implementation, Verification and Challenges; Vladimir Herdt1,2* & Rolf Drechsler1,2; 1Institute of Computer Science, University of Bremen, Bremen 28359, Germany; 2Cyber-Physical Systems, DFKI GmbH, Bremen 28359, Germany, In Journal Science China Information Sciences (SCIS) - https://www.springer.com/journal/11432, 2021
  47. Automated Detection of Spatial Memory Safety Violations for Constrained Devices, Sören Tempel1 Vladimir Herdt1;2 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, ASP-DAC 2022
  48. Keynote: Towards Trustworthy RISC-V Processors for Safety-critical Applications, Eyck Jentzsch (MINRES Technologies, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  49. The TETRISC SoC for safety critical applications, Markus Ulbricht (IHP, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  50. Extending the RISC-V LLVM backend to Support Fault-tolerant Computing, Uzair Sharif (Technical University of Munich, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  51. Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes, Sören Tempel (University of Bremen, D), Vladimir Herdt (University of Bremen / DFKI, D), Rolf Drechsler (University of Bremen / DFKI, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  52. Setting up a debug solution with Lauterbach Debug Hardware and Software for a custom implementation of a RISC-V core - Lessons Learned, Zhao Han (Infineon, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  53. Panel: The RISC-V Software Ecosystem: Where we are and where are we going?, Ingo Feldner (Bosch, D), Drew Fustini (Beagleboard, US), Mark Himelstein (RISC-V International, CH), Philipp Tomisch (TU Vienna and VRULL GmbH, AT) 4th Workshop on RISC-V Activities, Online, 02.12.2021
  54. An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors; Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Fellow, IEEE, Dominik Stoffel, Wolfgang Kunz, Fellow, IEEE in IEEE Transactions on Computers, 2022
  55. RISC-V Processor Verification with Coverage-guided Aging; Niklas Bruns1, Vladimir Herdt1;2, Eyck Jentzsch3, Rolf Drechsler1;2; 1Institute of Computer Science, University of Bremen, Germany; 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany; 3MINRES Technologies GmbH, 85579 Neubiberg, Germany; MBMV 2022, Online, 17.2.2022
  56. A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI, Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, and Wolfgang Ecker Infineon Technologies AG, Munich, Germany, MBMV 2022, Online, 17.2.2022
  57. Constraints for Automatic, Generic SBST Generation for RISC-V Using SAT-Solving; Tobias Faller, Markus Schwörer, Philipp Scholl, Tobias Paxian, and Bernd Becker; Chair of Computer Architecture University of Freiburg, TuZ 2022, Bremerhaven, 27.02. bis 01.03.2022
  58. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging, Niklas Bruns1 Vladimir Herdt1;2 Eyck Jentzsch3 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany, 3MINRES Technologies GmbH, 85579 Neubiberg, Germany; DATE 2022, 14.3-23.3.2022; Online
  59. The Scale4Edge RISC-V Ecosystem, Wolfgang Ecker, Infineon Technologies AG; Milos Krstic, IHP –Leibniz Institut für innovative Mikroelektronik & University Potsdam; Andreas Mauderer, Robert Bosch GmbH; Eyck Jentzsch, MINRES Technologies GmbH; Mihaela Damian, Julian Oppermann, Andreas Koch, Technical University of Darmstadt; Peer Adelt, Wolfgang Müller, Paderborn University; Vladimir Herdt, Rolf Drechsler, University of Bremen / DFKI GmbH; Rafael Stahl, Karsten Emrich, Daniel Müller-Gritschneder, Technical University of Munich; Jan Schlamelcher, Kim Grüttner, OFFIS - Institut für Informatik; Jörg Bormann, Siemens EDA; Wolfgang Kunz, Technische Universität Kaiserslautern; Reinhold Heckmann, AbsInt Angewandte Informatik GmbH; Gerhard Angst, Ralf Wimmer, Concept Engineering GmbH; Bernd Becker, Philipp Scholl, Albert-Ludwigs-Universität Freiburg; Paul Palomero Bernardo, Oliver Bringmann, Universität Tübingen; DATE 2022, 14.3-23.3.2022; Online