Veröffentlichungen

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  • Best Paper Award Candidate:
    Processor Verification using Symbolic Execution: A RISC-V Case-Study
    ; Niklas Bruns, Vladimir Herdt and Rolf Drechsler; Universität Bremen, Design, Automation and Test in Europe (DATE) Conference 2023
  • Lu, J.-C. Chen, M. Ulbricht, M. Krstic, "Identifying Critical Flip-flops in Circuits with Graph Convolutional Networks", Proc. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2022
  • Lu, J. Chen, M. Ulbricht and M. Krstic, "A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional Networks", 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp. 20-25, doi: 10.1109/ISVLSI54635.2022.00017.
  • Sarić, J. Chen, E. Čustović, G. Panić, J. Kevrić, D. Jokić, M. Krstić, "Design of ASIC and FPGA system with Supervised Machine Learning Algorithms for Solar Particle Event Hourly Prediction", in IFAC-PapersOnLine, Volume 55, Issue 4, pp. 230-235, 2022, doi: 10.1016/j.ifacol.2022.06.038.
  • Lu, J. Chen, A. Breitenreiter, O. Schrape, M. Ulbricht and M. Krstic, "Machine Learning Approach for Accelerating Simulation-based Fault Injection", 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-6, doi: 10.1109/NorCAS53631.2021.9599646.
  • Chen, T. Lange, M. Andjelkovic, A. Simevski, L. Lu and M. Krstic, "Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning", in IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 2, pp. 564-580, 1 April-June 2022, doi: 10.1109/TETC.2022.3147376.
  • Transformative Hardware Design following the Model-Driven Architecture Vision, Zhao Han1,2, Gabriel Rutsch1, Deyan Wang1,2, Bowen Li1,2, Sebastian Siegfried Prebeck1,2, Daniela Sanchez Lopera1,2,Keerthikumara Devarajegowda1, and Wolfgang Ecker1,2; 1 Infineon Technologies AG, Germany; 2 Technical University Munich, Germany; Part of Springer Book
  • Bringing TinyML to RISC-V With Specialized Kernels and a Static Code Generator Approach, Rafael Stahl (Technical University of Munich), embedded World, Nuremberg, Germany, 21.6.2022
  • MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler. DESTION 2021, virtuell.
  • MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler, University Booth, DATE 2021, virtuell.
  • Rafael Stahl, „Utilizing Static Code Generation in TinyML“, in “tinyML EMEA Technical Forum”, June 2021, https://www.tinyml.org/event/emea-2021/, Recording available: https://youtu.be/ix_J5E_SIog
  • Schrape, M. Andjelković, A. Breitenreiter, S. Zeidler, A. Balashov and M. Krstić, "Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 11, pp. 4796-4809, Nov. 2021, doi: 10.1109/TCSI.2021.3109080.
  • Sarić et al., "Classification of Space Particle Events using Supervised Machine Learning Algorithms," 2021 IEEE 8th International Conference on Data Science and Advanced Analytics (DSAA), 2021, pp. 1-10, doi: 10.1109/DSAA53316.2021.9564114.
  • https://github.com/fzi-forschungszentrum-informatik/chips-core - Das CHIPS-Framework ist eine in Scala eingebettete domänenspezifische Sprache (DSL), die die Spezifikation von leichtgewichtigen Verifikationseigenschaften auf verschiedenen Abstraktionsebenen unter Verwendung des assertion-basierten Verifikationsparadigmas ermöglicht; Open Source
  • https://github.com/fzi-forschungszentrum-informatik/firrtl-ast - Rust-Bibliothek, welche eine FIRRTL-AST-Darstellung und zugehörige Managementschnittstellen, einschließlich eines Parsers und Formatierers, bereitstellt; Open Source
  • CHIPS: A Property Specification and Verification Framework for RISC-V based System-on-Chip (SoC) Designs; A. Paule, O. Bringmann, MBMV 2021 Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
  • Deligiannis N. I., Cantoro, R., Faller T., Paxian T., Becker B., & Sonza Reorda, M.; Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor, In 2021 IEEE 30th Asian Test Symposium (ATS) (pp. 73-78).
  • Faller, Tobias, et al. "Towards SAT-Based SBST Generation for RISC-V Cores" In 2021 IEEE 22nd Latin American Test Symposium (LATS). IEEE, 2021.
  • Hardware-aware Edge AI using the parameterizable ML accelerator UltraTrail, Paul Palomero Bernardo, tinyML Talks, September 22, 2021
  • Scale4Edge RISC-V Computing Ecosystem: Virtual Prototyping First!, Wolfgang Ecker, Daniel Mueller-Gritschneder, Ingo Feldner, Vladimir Herdt, Eyck Jentzsch, Christian Mayr, Oliver Bringmann, Johannes Partzsch, Paul Palomero Bernardo, Embedded IoT World 2021, March 30-31 2021
  • Wolfgang Ecker organisierte die Session “Industrial Sesson: RISC-V: Evolution, Innovation and Research Challenges of Open-ISA” zur IEEE 35th International System-on-Chip Conference (SOCC) ; Titanic, Belfast, Northern Ireland, September 5-8, 2022; https://edas.info/p29519#S1569607348; https://www.ieee-socc.org/
  • An Industrial Perspective on RISC-V Innovation by Keerthikumara Devarajegowda, Sebastian Prebeck, Endri Kaja, Nicolas Gerlin, Sven Wenzeck, Daniela Sanchez Lopera, Wolfgang Ecker from Infineon Technologies; IEEE 35th International System-on-Chip Conference (SOCC); Titanic, Belfast, Northern Ireland, September 5-8, 2022
  • SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification, Sören Tempel1, Vladimir Herdt1,2, and Rolf Drechsler1,2, 1 Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, 2 Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany, ATVA 2022, Oct 25, 2022 - Oct 28, 2022, Beijing, China
  • Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification, 1st Niklas Bruns, Institute of Computer Science University of Bremen, Bremen, Germany, 2nd Vladimir Herdt, Institute of Computer Science University of Bremen, Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, 3rd Rolf Drechsler, Institute of Computer Science, University of Bremen, Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, FDL 2022, September 14–16, 2022, Linz, Austria
  • 3D Visualization of Symbolic Execution Traces, Jan Zielasko1 S¨oren Tempel2 Vladimir Herdt1,2 Rolf Drechsler1,2, 1Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany, 2Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, FDL 2022, September 14–16, 2022, Linz, Austria
  • CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation Conrad Foik, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Technical University of Munich, Germany, FDL 2022, September 14–16, 2022, Linz, Austria
  • Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting; ANSELM BREITENREITER1, MARKO ANDJELKOVIC1, OLIVER SCHRAPE1 AND MILOS KRSTIC1,2; 1IHP – Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany, 2University of Potsdam, Potsdam, Germany; Corresponding author: Anselm Breitenreiter in IEEE Access, vol. 10, pp. 51814-51825, 2022, doi: 10.1109/ACCESS.2022.3174564.
  • Breitenreiter, M. Andjelković, O. Schrape and M. Krstić, "Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting",.
  • Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing; Sören Tempel1, Vladimir Herdt1,2, Rolf Drechsler1,2, 1Institute of Computer Science, University of Bremen; 2Cyber-Physical Systems, DFKI GmbH, Bremen; IEEE Embedded Systems Letters (ESL) journal; 2022
  • Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools; Pascal Pieper1, Vladimir Herdt12, Daniel Große3, Rolf Drechsler12; 1Cyber-Physical Systems, DFKI GmbH, Bremen, Germany; 2 Institute of Computer Science, University of Bremen, Bremen, Germany; Institute for Complex Systems, Linz, Austria; DAC 2022, 10.-14.7.2022
  • SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors; Mihaela Damian1, Julian Oppermann1, Christoph Spang1, Andreas Koch1; 1Technical University Darmstadt, Darmstadt, Germany; DAC 2022, 10.-14.7.2022
  • Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing, Lucas Deutschmann, Johannes Müller, Mohammad R. Fadiheh, Dominik Stoffel, Wolfgang Kunz, TU Kaiserslautern, DAC 2022, 10.-14.7.2022
  • DAC-2022 Best Paper Award:
  • Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype; Pascal Pieper1, Vladimir Herdt12, Rolf Drechsler12, 1Cyber-Physical Systems, DFKI GmbH, 2Institute of Computer Science, University of Bremen; GLSVLSI 2022; June 6-8, 2022, Irvine, CA, US
  • Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing; Niklas Bruns1, Vladimir Herdt12, Daniel Große23, Rolf Drechsler12, 1Institute of Computer Science, University of Bremen 2Cyber-Physical Systems, DFKI GmbH, 3Johannes Kepler University; GLSVLSI 2022; June 6-8, 2022, Irvine, CA, US
  • SymEx-VP: An Open Source Virtual Prototype for OS-Agnostic Concolic Testing of IoT Firmware; Sören Tempel1 Vladimir Herdt1,2 Rolf Drechsler1,2; 1Institute of Computer Science, University of Bremen, Bremen, Germany; 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany; Journal of Systems Architecture (JSA); Vol. 125; April 2022; https://doi.org/10.1016/j.sysarc.2022.102456.
  • The Scale4Edge RISC-V Ecosystem, Wolfgang Ecker, Infineon Technologies AG; Milos Krstic, IHP –Leibniz Institut für innovative Mikroelektronik & University Potsdam; Andreas Mauderer, Robert Bosch GmbH; Eyck Jentzsch, MINRES Technologies GmbH; Mihaela Damian, Julian Oppermann, Andreas Koch, Technical University of Darmstadt; Peer Adelt, Wolfgang Müller, Paderborn University; Vladimir Herdt, Rolf Drechsler, University of Bremen / DFKI GmbH; Rafael Stahl, Karsten Emrich, Daniel Müller-Gritschneder, Technical University of Munich; Jan Schlamelcher, Kim Grüttner, OFFIS - Institut für Informatik; Jörg Bormann, Siemens EDA; Wolfgang Kunz, Technische Universität Kaiserslautern; Reinhold Heckmann, AbsInt Angewandte Informatik GmbH; Gerhard Angst, Ralf Wimmer, Concept Engineering GmbH; Bernd Becker, Philipp Scholl, Albert-Ludwigs-Universität Freiburg; Paul Palomero Bernardo, Oliver Bringmann, Universität Tübingen; DATE 2022, 14.3-23.3.2022; Online
  • Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging, Niklas Bruns1 Vladimir Herdt1;2 Eyck Jentzsch3 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany, 3MINRES Technologies GmbH, 85579 Neubiberg, Germany; DATE 2022, 14.3-23.3.2022; Online
  • ZuSE Scale4Edge: Entwicklungsplattform und Ökosystem für skalierbare Spezialprozessoren im Edge-Computing - Das etwas andere Projekt, Wolfgang Ecker, Infineon Technologies, Digitale Fachkonferenz „Vertrauenswürdige Elektronik 2022“, 9.3.2022
  • Gewinner des Nachwuchswettbewerbs zur Digitale Fachkonferenz „Vertrauenswürdige Elektronik 2022“: Rahmani Fadiheh (Technische Universität Kaiserlautern): Microarchitectural side channels and security-critical design bugs: Towards a unified approach for RTL Hardware verification, 9.+10.3.2022, Online
  • Constraints for Automatic, Generic SBST Generation for RISC-V Using SAT-Solving; Tobias Faller, Markus Schwörer, Philipp Scholl, Tobias Paxian, and Bernd Becker; Chair of Computer Architecture University of Freiburg, TuZ 2022, Bremerhaven, 27.02. bis 01.03.2022
  • A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI, Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, and Wolfgang Ecker Infineon Technologies AG, Munich, Germany, MBMV 2022, Online, 17.2.2022
  • RISC-V Processor Verification with Coverage-guided Aging; Niklas Bruns1, Vladimir Herdt1;2, Eyck Jentzsch3, Rolf Drechsler1;2; 1Institute of Computer Science, University of Bremen, Germany; 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany; 3MINRES Technologies GmbH, 85579 Neubiberg, Germany; MBMV 2022, Online, 17.2.2022
  • An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors; Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Fellow, IEEE, Dominik Stoffel, Wolfgang Kunz, Fellow, IEEE in IEEE Transactions on Computers, 2022
  • Automated Detection of Spatial Memory Safety Violations for Constrained Devices, Sören Tempel1 Vladimir Herdt1;2 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, ASP-DAC 2022, 17.-20.1.2022
  • Panel: The RISC-V Software Ecosystem: Where we are and where are we going?, Ingo Feldner (Bosch, D), Drew Fustini (Beagleboard, US), Mark Himelstein (RISC-V International, CH), Philipp Tomisch (TU Vienna and VRULL GmbH, AT) 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • Setting up a debug solution with Lauterbach Debug Hardware and Software for a custom implementation of a RISC-V core - Lessons Learned, Zhao Han (Infineon, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes, Sören Tempel (University of Bremen, D), Vladimir Herdt (University of Bremen / DFKI, D), Rolf Drechsler (University of Bremen / DFKI, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • Extending the RISC-V LLVM backend to Support Fault-tolerant Computing, Uzair Sharif (Technical University of Munich, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • The TETRISC SoC for safety critical applications, Markus Ulbricht (IHP, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • Keynote: Towards Trustworthy RISC-V Processors for Safety-critical Applications, Eyck Jentzsch (MINRES Technologies, D), 4th Workshop on RISC-V Activities, Online, 02.12.2021
  • Advanced Virtual Prototyping for Cyber-Physical Systems using RISC-V: Implementation, Verification and Challenges; Vladimir Herdt1,2* & Rolf Drechsler1,2; 1Institute of Computer Science, University of Bremen, Bremen 28359, Germany; 2Cyber-Physical Systems, DFKI GmbH, Bremen 28359, Germany, In Journal Science China Information Sciences (SCIS) - https://www.springer.com/journal/11432, 2021
  • Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead, Oliver Bringmann1, Wolfgang Ecker2, Ingo Feldner3, Adrian Frischknecht1,Christoph Gerum1,Timo Hämäläinen4, Muhammad Abdullah Hanif5, Michael J. Klaiber3, Daniel Müller-Gritschneder6, Paul Palomero Bernardo1,Sebastian Prebeck2, Muhammad Shafique7; 1 University of Tübingen, 2 Infineon Technologies AG, 3 Bosch Corporate Research, 4 Tampere University, 5 Technische Universität Wien, 6 Technical University of Munich, 7 New York University Abu Dhabi, Special Session, ESWEEK 2021, Virtual Conference, October 10 – 15, 2021
  • Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level, Frank Riese1 Vladimir Herdt1;2 Daniel Große3 Rolf Drechsler1;2 1Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany 2Institute of Computer Science, University of Bremen, , Germany 3Institute for Complex Systems, Johannes Kepler University Linz, Austria, VLSI SoC 2021, virtuell
  • In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes, Sören Tempel, Vladimir Herdt, Rolf Drechsler. FDL 2021, Antibes, France.
  • RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler. FDL 2021, Antibes, France.
  • Johannes Müller, Mohammad R. Fadiheh, Anna Duque Anton, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz :“A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level”, IEEE/ACM Design Automation Conference (DAC), Dec. 5-9, 2021, San Francisco/virtual, USA. (accepted)
  • Intel Hardware Security Academic Award 2022 (https://www.intel.com/content/www/us/en/security/security-practices/secu...):
  • Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V, Rafael Stahl, Technical University of Munich, RISC-V Forum on "Developer Tools & Tool Chains", 2.6.2021; https://riscvforumdttc2021.sched.com/event/jGkT, Recording available: https://youtu.be/NLGAjdVIzkk
  • Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform, Vladimir Herdt1;2 Daniel Große2;3 Sören Tempel1 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, 3Institute for Complex Systems, Johannes Kepler University Linz, Austria in Journal of Systems Architecture (JSA), Elsvier, 2021
  • Krishnamurthy, Pradeep, & Poppen, Frank. (2021, May 17). Implementing VexRiscv Based Murax SoC on Arty A7 Artix-7 PCB from Digilent and Enabling JTAG Connection through Xilinx's BSCANE2 Debug IP. Zenodo. http://doi.org/10.5281/zenodo.4767195
  • μRV32: An Open Source RISC-V Cross-Level Platform for Education and Research, Sallar Ahmadi-Pour1, Vladimir Herdt1,2, Rolf Drechsler1,2, 1University of Bremen, 2DFKI GmbH Bremen, Germany, DESTION 2021, 18.5.2021.
  • New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core, Nikolaos I. Deligiannis1, Riccardo Cantoro1, Matthias Sauer3, Bernd Becker2, Matteo Sonza Reorda1, 2 of Freiburg - Freiburg, Germany, 1Politecnico di Torino, DAUIN - Torino, Italy, 3Advantest - Böblingen, Germany, 26-28.4.2021, IEEE VTS 2021, Virtual
  • FZI plant ein Arbeitsergebnis aus Scale4Edge auf dem MBMV-Workshop im Rahmen einer live Demonstration, am 19.03.2021, zu präsentieren. Für die Veröffentlichung und zur besseren Einsichtnahme findet sich das Werkzeug auf GitHub: https://github.com/fzi-forschungszentrum-informatik/chips-core. Hierbei handelt es sich um die CHIPS (Chisel Hardware Property Specification) Sprache sowie unterstützendes Tooling.
  • Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing, Universität Bremen, DAC 2021, December 5-9, 2021, virtual
  • Towards RISC-V CSR Compliance Testing, Niklas Bruns, Vladimir Herdt, Daniel Große, Senior Member, University of Bremen, IEEE and Rolf Drechsler, Fellow, IEEE; IEEE EMBEDDED SYSTEMS LETTERS (ESL) journal, VOL. 13, NO. 1, MARCH 2021
  • Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion, Sallar Ahmadi-Pour1, Vladimir Herdt1;2, Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, MBMV, Virtuell, 18.-19.3.2021.
  • Register and Instruction Coverage Analysis for Different RISC-V ISA Modules, Peer Adelt, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, Heinz Nixdorf Institut/Universität Paderborn, Paderborn, Germany, MBMV, Virtuell, 18.-19.3.2021.
  • On Self-Verifying DSL Generation for Embedded Systems Automation, Zhao Han1,2, Shahzaib Qazi2, Michael Werner1,2, Keerthikumara Devarajegowda1,3, Wolfgang Ecker1,2, Infineon Technologies AG1 - Technical University Munich2 - Technical University Kaiserslautern3, MBMV, Virtuell, 18.-19.3.2021.
  • Extending Verilator to enable Fault simulation, Endri Kaja1,2, Nicolas Ojeda Leon1,4, Michael Werner1,3, Bogdan Andrei-Tabacaru1, Keerthikumara Devarajegowda1, Wolfgang Ecker1,3, 1Infineon Technologies AG, Germany, 2Technische Universität Kaiserslautern, Germany, 3Technische Universität München, Germany, 4Darmstadt University of Applied Sciences, Germany, MBMV, Virtuell, 18.-19.3.2021.
  • An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes, Sören Tempel1 Vladimir Herdt1;2 Rolf Drechsler1;2, 1Institute of Computer Science, University of Bremen, Bremen, Germany, 2Cyber-Physical Systems, DFKI GmbH, Bremen, Germany, DATE 2021
  • Vortrag und Panel Diskussion: Wolfgang Ecker “European collaboration: Scale4Edge project introduction”, SOC HUB LAUNCH – BOOST COMPETITIVENESS THROUGH SYSTEM-ON-CHIP at Tampere. Smart City Week, Online, 27.01.2021, https://smarttampere.fi/en/home/
  • Vladimir Herdt, Sören Tempel, Daniel Große, and Rolf Drechsler. Mutation-based Compliance Testing for RISC-V. In 26th Asia and South Pacific Design Automation Conference (ASPDAC ’21), January 18–21, 2021, Tokyo, Japan. ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3394885.3431584
  • ICCD 2020: "Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime", UB
  • ATVA 2020: "RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms", UB
  • GLSVLSI 2020: "Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes", UB
  • Vortrag auf der Onespin User-Konferenz OSMOSIS 2020: W. Kunz: “Hardware Security Verification using Unique Program Execution Checking”, 1.-2.12.2020, (virtuell).
  • Kunz, M. Fadiheh: “A Formal RTL Verification Approach for Detecting Transient Execution Side Channels in Processors”, Intel – IPAS Tech Sharing Forum, Dezember, 2020
  • RISC-V Summit 2020 with "Scale4Edge project introduction" by Wolfgang Ecker, Lead Principle Engineer, Infineon Technologies, Virtual Event, Tuesday, 8 December 2020 12:00pm - 12:20pm - PST (Pacific Standard Time, GMT-8); https://tmt.knect365.com/risc-v-summit/
  • UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting by Paul Palomero Bernardo, Christoph Gerum, Adrian Frischknecht, Konstantin Lübeck, and Oliver Bringmann, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, Issue: 11, Nov. 2020, http://dx.doi.org/10.1109/TCAD.2020.3012320.
  • Ecker: Vorstellung von Scale4Edge von auf der EFECS 2020, 25.-26.11.2020
  • Security Issues in Hardware/Firmware interaction – Can a formal analysis of (just) the hardware help?, Johannes Müller (Technical University of Kaiserslautern, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • A Configurable Virtual Prototyping Environment for Different RISC-V ISA Subsets, Peer Adelt (University of Paderborn, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • Efficient RISC-V Processor Verification via Cross-Level Testing, Vladimir Herdt (University of Bremen / DFKI, D), Eyck Jentzsch (MINRES Technologies, D), Daniel Große (Johannes Kepler University Linz, AT), Rolf Drechsler (University of Bremen / DFKI, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • A Compiler Comparison in the RISC-V Ecosystem, Mehrdad Poorhosseini, Kim Grüttner, Wolfgang Nebel (OFFIS, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • Energy Efficient RISC-V Implementations in 22 nm, Heiner Bauer (Technical University of Dresden, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • A RISC-V based Edge Computing Platform with Interchangeable Cores Using 22FDX, Paul Palomero Bernardo, Adrian Frischknecht, Dustin Peterson, University of Tuebingen, D, Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • Keynote: Invited Talk: RISC-V Scale4Edge Ecosystem - Motivation and Objectives, Wolfgang Ecker (Infineon, D), Workshop on RISC-V Activities 2020, 8.10.2020, Virtuell
  • Organisation RISC-V Workshop am 8.10.2020
  • Von TUK wurden vier Vortragsbeiträge zum Intel internen SCAP Workshop 2020 (virtuell) eingeladen und geleistet, 28.9.-1.10.2020.
  • Pressemitteilung OSS mit TUK, RB und MNRS, im September 2020
  • Pressemitteilung IFX, am 24. September 2020 „Projekt Scale4Edge startet im Rahmen der Leitinitiative „Vertrauenswürdige Elektronik“ des Bundesforschungsministeriums - Skalierbares Ökosystem für Spezialprozessoren für das Internet der Dinge wird angestrebt“ (https://www.infineon.com/cms/de/about-infineon/press/press-releases/2020...)
  • Ecker: ZuSE Workshop am 22.9.2020
  • Best Paper Award: "Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study", Vladimir Herdt, Daniel Große, Universität Bremen, DE, Eyck Jentzsch, MINRES Technologies GmbH, DE, Rolf Drechsler, Universität Bremen, DE, FDL 2020, September 2020
  • Ecker: Silicon Saxony: Vortrag am 11.9.2020
  • Pressemeldung der TU Kaiserslautern am 6.7.2020
  • Ecker: Pressekonferenz „Vertrauenswürdige Elektronik“ am 9.6.2020
  • HNI Newsletter Ausgabe 01 2020 der Universität Paderborn „Neues Verbundprojekt Scale4Edge“. S.8: https://www.hni.uni-paderborn.de/fileadmin/Publikationen/hni_aktuell/hni_aktuell_1_2020.pdf