Sergio Marchese, OneSpin Solutions, GB
Abstract
RISC-V is leading the open-source hardware revolution. Individuals, companies, and not-for-profit organizations such as the Open Hardware Group are contributing RTL cores, simulators, toolchain software, and verification testbenches and results. Hardware security is crucial for a wide range of applications, from IoT to connected autonomous vehicles and other safety-critical systems. Open-source RISC-V cores offer both security challenges and opportunities. Processor cores provide fertile soil for the insertion of hardware Trojans. Complex pipeline implementations chasing performance, power, and area targets are a great hiding place for malicious logic, bugs, and unforeseen misuse cases. Pre-silicon RTL verification focuses on intended use cases and still misses bugs routinely. Malicious actors, on the other hand, may deliberately search for unintended behaviors and misuse cases exploitable in security attacks. Scrutiny from the broad engineering community can potentially provide a level of trustworthiness assurance that no proprietary core can match. This presentation reports on security and trust assurance contributions made for the open-source cores RocketCore and OpenHW CV32E. Using a RISC-V ISA model expressed in SystemVerilog and formal verification technology, the authors were able to detect and report security-relevant bugs and undocumented, non-standard functions.
Biography
Sergio Marchese is technical marketing manager at OneSpin Solutions. He has 20 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high-integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.
https://www.linkedin.com/in/sergiomarchese/ [1]
