edaForum05 Presentation
Company Presentation Mentor Graphics Corp.
"Hot Spots in IC Nanometer Design"
Abstract
A unique convergence of intense pressures is threatening the viability of cheaper, smaller, faster that has driven the high tech industry for decades. However we have seen a slow-down of the ramp-up speed of new technologies. As mainstream design moves squarely into the nanometer realm, designers must contend with numerous deep submicron effects due to device physics. And lower power consumption is emerging as a critical limiting factor for next-generation applications.
At the same time, the spiraling complexity of SoCs with millions of gates, mixed signal capabilities and increasingly data-intensive performance is leading to design and verification overload, pushing development costs up significantly. Non recurrent engineering costs of 30 Million US-Dollar per System on Chip are quite common.
In his presentation these hot spots and their consequences on the increasing pressure of the design teams will be examined. The designer is mutating into a verification engineer for the majority of his time. He has to bare in mind all sorts of impacts his design will have on the following manufacturing processes. Besides the power awareness the main buzzwords here are Design-for-Manufacturing , Design-for-Yield , Design for Test Promising EDA technologies focused on alleviating the pressures on today s design teams will be discussed as well. For example, next-generation design and verification capabilities are raising the level of abstraction to manage increasing complexity and the need for more algorithmic-centric performance. Together with higher-level verification technologies, they will enable designers to create more cost-effective nanometer ICs. As for physical design, the combination of advanced design for manufacturing and test capabilities is promoting higher yields and faster time to production. Power-aware design flows, for both the front and backend, are becoming a reality today.
