Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

DruckversionPer E-Mail sendenPDF-Version
3D-Test
in conjunction with ITC / Test Week 2013
September 12-13, 2013 - Disneyland Hotel – Anaheim, California, USA
 

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

http://3dtest.tttc-events.org/