Using Synopsys VCS to connect a Company’s SystemC Verification Methodology to Standard Concepts of UVM

Authors: Frank Poppen, OFFIS - Institut für Informatik, DE; Marco Trunzer, Robert Bosch GmbH, DE; Jan-Hendrik Oetjens, Robert Bosch GmbH, DE


Over the last decades, intelligent electronics in heterogeneous systems improved all aspects of everyone’s daily life. An advantage a modern civilization cannot ignore. The increasing complexity of the electronic components though, makes us dependent on solving a growing design verification challenge. Especially knowing, that safety relevant functionality as in automotive driving is part of this development. Standardized as well as proprietary concepts, languages and tools line up for the task [6]. Unfortunately, there is no such thing as one size fits all in this. Verification engineers need to choose and combine what fits best for the company, the design-team and application domain. They create company’s verification strategies with deep roots into the design process. Changes to the strategy need to be done carefully and incrementally to ensure continued productivity. This work is a twin of the previously published paper [1] and a copy of that in big parts enhanced by more code examples in the Appendixes A to C. In [1] we compared concepts of UVM [9] and showed how UVM components are instantiable in our SystemC (SC) based IFS [3] test environment using UVM Connect to verify designs specified in VHDL (-AMS), SystemC (-AMS), Verilog (-AMS) or Matlab/Simulink [4]. There we demonstrated that our approach and UVMC do not depend on proprietary technology and presented the applicability for mixed language simulators from Mentor and Cadence. This paper is to extend the claim to cover Synopsys vcs-mx as another mixed language simulation environment: we make use of SystemVerilog UVM inside a SystemC test bench connected with UVMC using Synopsys’ simulator vcs-mx.

Publication Date: 2015/06/25

Location of Publication: SNUG Germany 2015

Keywords: Automotive; System Design