[AN07] Agarwal, Nassif: Characterizing Process Variation in Nanometer CMOS, DAC, 2007.
[BNS06] F. De Bernardinis, P. Nuzzo, A. Sangiovanni-Vincentelli: Robust System Level Design with Analog Platforms, International Conference on Computer Aided Design (ICCAD’06), November 2006.
[Bun06] Deutscher Bundestag: Aktionsprogramm für Straßenverkehrssicherheit: Halbierung der Zahl der Unfallopfer bis 2010, http://www.bundestag.de/ausschuesse/a15/berichte/16-578.pdf, 2006
[CLL+07] Cheng, Lin, Lee, Chiu, Wu: Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration, International Physics Symposium, 2007.
[CSW07] Coskun, Simunic-Rosing, Whisnant: Temperature-Aware Task Scheduling in MPSoCs, DATE, 2007.
[GET+06] Grasser, Entner, Triebl, Enichlmair, Minixhofer: TCAD Modeling of Negative Bias Temperature Instability, International Conference on Simulation of Semiconductor Processes and Devices, 2006.
[Gre03] D. Grell: Rad am Draht, Innovationslawine in der Autotechnik, http://www.heise.de/ct/03/14/170/, ct Online, 2003.
[Gre05] D. Grell: Computer on the Road, Innovationslawine in der Autotechnik, Teil 1, http://www.heise.de/autos/suche/?rm=result;q=elektronik;url=/autos/artikel/3652/;words=Elektronik, ct-Online, 2005.
[HiTech] BMBF, Die Hightech-Strategie für Deutschland, http://www.bmbf.de/pub/bmbf_hts_lang.pdf
[HTS07] Humenay, Tarjan, Skadron: Impact of Process Variations on Multicore Performance Symmetry, DATE, 2007.
[IKT2020] BMBF, IKT 2020, http://www.bmbf.de/pub/ikt2020.pdf.
[JaFr08] R. Jancke, R. Frevert, C. Ellmers, R. Gaertner: Abschätzung von Bauelemente-Lebensdauer und SOA-Grenzen zur Unterstützung des Entwurfs zuverlässiger Schaltungen, ZUE 2008.
[KKS07] S. Kumar, C. Kim, S. Sapatnekar: NBTI-Aware Synthesis of Digital Circuits, ACM/IEEE Design Automation Conference (DAC), 2007.
[Krep08] D. Krepper: Zulieferer revolutionieren die Autobranche, http://www.spiegel.de/wirtschaft/0,1518,554146,00.html.
[LMM06] Z. Liu, B. W. McGaughy, J. Z. Ma: Design Tools for Reliability Analysis, ACM/IEEE Design Automation Conference (DAC), 2006.
[LQH+06] Li, Qin, Huang, Zhang, Bernstein: SRAM circuit-failure modeling and reliability simulation with SPICE, Transactions on Device and Materials Reliability, June 2006.
[McG07] B. W. McGaughy (Cadence Design Systems), Personal Communication, November 2007.
[McP06] McPherson: Reliability Challenges for 45nm and Beyond, DAC, 2006.
[MMA+07] Murali, Mutapcic, Atienza, Gupta, Boyd, De Micheli: Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization, CODES+ISSS, 2007.
[PMW+06] Papanikolaou, Miranda, Wang, Catthoor, Satyakiran, Marchal, Kaczer, Bruynseraede,Tokei: Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design, VLSISOC, 2006.
[PPI+07] Pop, Poulsen, Izosimov, Eles: Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems, CODES+ISSS, 2007.
[Ro+01] G. L. Rosa et al.: New phenomena in device reliability physics of advanced CMOS submicron technologies, IEEE International Reliability Physics Symposium (IRPS) tutorial, 2001.
[Royc97] J. Roychowdhury: Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits. DAC 1997.
[SAB+03] Srinivasan, Adve, Bose, Rivers, Hu: RAMP: A Model for Reliability Aware Micro Processor Design, IBM Research Report, 2003.
[SAB+04] Srinivasan, Adve, Bose, Rivers: The Impact of Technology Scaling on Lifetime Reliability, DSN, 2004.
[Sei06] Seifert: Extending
[SWK+05] Saggese, Wang, Kalbarczyk, Patel, Iyer: An Experimental Study of Soft Errors in Microprocessors, IEEE Micro, November 2005.
[TMA+05] Tosun, Mansouri, Arvas, Kandemir, Xie: Reliability-Centric High-Level Synthesis, DATE, 2005
[WFY+00] L. Wu et al.: GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design, International Symposium on Quality of Electronic Design, 2000.
[Win07] H. Winner: Mercedes und der Elch: Die perfekte Blamage, http://www.welt.de/motor/article1280688/Mercedes_und_der_Elch_Die_perfekte_Blamage.html.
[ZTB06] M. H. Zaki, S. Tahar, G. Bois: A Practical Approach for Monitoring Analog Circuits, Proceedings of the Great Lakes Symposium on VLSI, Mai 2006.
OFFIS
[NHK06] W. Nebel, D. Helms, A. Keshavarzi: Leakage Currents in Nanometer CMOS, ISLPED Embedded Tutorial 2006.
[HEN06] D. Helms, G. Ehmen, W. Nebel: Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation, ISLPED 2006.
[HNN06] D. Helms, M. Hoyer, W. Nebel: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage, PATMOS 2006.
[RHN07] S. Rosinger, D. Helms, W. Nebel: RTL Power Modeling and Estimation of Sleep Transistor based Power Gating, PATMOS 2007.
[HHN07] M. Hoyer, D. Helms, W. Nebel: Modelling the impact of high level leakage optimization techniques on the delay of RT-components, PATMOS 2007.
[HHR+08] D. Helms, M. Hoyer,
FZI
[VSB+08] A. Viehl, B. Sander, O. Bringmann, W. Rosenstiel: Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties, Forum on specification & Design Languages (FDL), Stuttgart, 2008.
[VSB+07] A. Viehl, M. Schwarz, O. Bringmann, W. Rosenstiel: Probabilistic Performance Risk Analysis at System-Level. Proceedings of 5th International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS),
[SBR07] B. Sander, O. Bringmann, W. Rosenstiel: Applikationsspezifische Zuverlässigkeitsbewertung von MPSoCs edaWorkshop, Hannover 2007.
[SZB+07] T. Schönwald, J. Zimmermann, O. Bringmann, W. Rosenstiel: Fully Adaptive Fault Tolerant Routing Algorithm for Network-on-Chip Architectures, Euromicro Conference on Digital System Design, Lübeck, 2007.
[BBR+06] A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, Herkersdorf: An Architecture for Runtime Evaluation of SoC Reliability, Lecture Notes in Informatics, 2006.
[LHR+05] G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele: Towards a Framework and a Design Methodology for Autonomic SoC, IEEE International Conference on Autonomic Computing, 2005.
UF
[KlBaHe06] R. Klausen, E. Barke, L. Hedrich, "Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen" 9. ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2006.
[JeLaPa07] A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Analog Simulation Meets Digital Verification - A Formal Assertion Approach for Mixed-Signal Verification", The 14th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'07), Oktober 2007.
[StHe08] S. Steinhorst, L. Hedrich, "Model Checking of Analog Systems using an Analog Specification Language", Proc. of the Conference on Design, Automation and Test in Europe 2008 (DATE'08), S.324-329, 2008.
[WaHe06] X. Wang, L. Hedrich, "Hierarchical Exploration and Selection of Transistor-Topologies for Analog Circuit Design", IEEE International Symposium on Circuits and Systems (ISCAS), May 2006.
US
[RS08] M. Radetzki, R. Salimi Khaligh: Accuracy-Adaptive Simulation of Transaction Level Models, In Proc. Design Automation and Test in
[Ra08] M. Radetzki: Fehlertoleranz in Networks-On-Chips mit Deflection Routing, Zur Veröffentlichung eingereicht, 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf.
LUH
[Zh07] M. Zhang, M. Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, E. Barke, "CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions", Design, Automation and Test in Europe (DATE2007), April 2007, pp. 243 248.
[Pa07] P. Panitz, M. Olbrich, E. Barke, J. Koehl, "Robust Wiring Networks for DfY Considering Timing Constraints", Great Lakes Symposium on VLSI 2007, March 2007, pp. 43-48.
[OlBa08] M. Olbrich, E. Barke: Distribution Arithmetic for Stochastical Analysis, ASPDAC 2008, January 2008, pp. 537-542.
[Gr08] D. Grabowski, M. Olbrich, E. Barke: Analog Circuit Simulation Using Range Arithmetics, ASPDAC 2008, January 2008, pp. 762-767.
[Hö08] S. Hölldampf, D. Zaum, M. Olbrich, E. Barke, S. Schmidt,
TUM
[AG03] K. Antreich, H. Graeb: Circuit optimization driven by worst-case distances, In: The Best of ICCAD - 20 Years of Excellence in Computer-Aided Design, Kluwer Academic Publishers, 2003.
[BK+06] M. Bühler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, A. Ripp: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design, DATE 2006, March 2006.
[SGS+04] U. Schlichtmann, H. Gräb, R. Sommer, E. Hennig, F. Schenkel, T. Ifstroem: Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD, MEDEA+ Forum, 2004.
[SJ06] P. Spindler, F. M. Johannes: Fast and Robust Quadratic Placement Based on an Accurate Linear Net Model, IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2006.
[SJS08] P. Spindler, F. M. Johannes, U. Schlichtmann: Kraftwerk2 A fast force-directed Quadratic Placement Approach Using an Accurate Net Model, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 8, August 2008.
[SKS08a] M. Schmidt, H. Kinzelbach, U. Schlichtmann: Variational Waveform Propagation for Accurate Statistical Timing Analysis, TAU Workshop, 2008.
[SKS08b] M. Schmidt, H. Kinzelbach, U. Schlichtmann: Genauere Laufzeitanalyse digitaler Schaltungen durch Berücksichtigung statistischer Schwankungen der Signalformen, edaWorkshop, 2008.
[SLSKS07] M. Schmidt, B. Li, W. Schneider, H. Kinzelbach and U. Schlichtmann: Statistical Timing Analysis using Weibull Waveform Modeling, International Symposium on Integrated Circuits, 2007.
[SSLS07] W. Schneider, M. Schmidt, B. Li, U. Schlichtmann: A New Bounding Technique for Handling Arbitrary Correlations in Path Based Statistical STA, edaWorkshop, 2007.
[SSS07] W. Schneider, M. Schmidt, U. Schlichtmann: Statistische Laufzeitmodellierung digitaler Gatter mittels analytischem Timing-Modell und Dichte-Transformationssatz, Zuverlässigkeit und Design, 2007.