Technical Session I
RF & MS Integration Challenges in Single Chips for Mobile Phone Applications
Werner Geppert, Infineon
Abstract
Starting with the 130 nm node, subtle physical effects lead to unexpected re-spins and drastically increased efforts in the device modeling and circuit design departments. Architectural changes to digitize analog functionality have been identified as one viable option to cope with these effects.
With the RF move from bipolar to CMOS and the following single chip integration new challenges were introduced such as 1/f noise and RF/digital interference. The later ones being extremely complex as the effects involve the die itself, the redistribution layer, more than 200 balls to be connected to the printed circuit board and the board itself.
Main driver of Moore's Law is to take advantage of higher complexity at lower pricing. Remaining still true for mostly digital products, products with a high content of Analog or RF circuits do not scale anymore in the same amount as the digital circuit portions, so that the cost advantage is decreasing. Even worse, moving functionality to the next node the die size might even become larger without the introduction of complete different architectures. In addition, the integration of functions like power management units on the same die needs special devices to deal with the high voltage requirements. Therefore, the economical benefit of brute force node to node migration has to be questioned.
Biography
Werner Geppert Head Design Methodology Communication Solutions Base Technologies and Servicess Infineon Technologies AG
Werner Geppert was born in Essen, Germany, 1964. He received his Dipl.- Ing. and Dr.-Ing. degrees in electrical engineering from Ruhr-University Bochum, Germany in 1991 and 1996, respectively. 1996 he joined the RF division of SIEMENS Semiconductors as RF circuit designer for cordless products. In 1998 he became responsible for RF design technology. In 1999 he took over the position as design center manager of the SIEMENS Microelectronics RF group in Princeton, NJ. Between 2002 and 2006 he held various engineering management positions within Infineon Germany, with main responsibility being the head of the RF & MS design methodology group of the communications division (COM). Since early 2006 he is the head of overall design methodology at COM which includes global teams for System-, RF/MS- as well as digital design methodology and global support teams as interface to all R&D projects.
