Dominik Sisejkovic, RWTH Aachen University, DE
Authors: Dominik Sisejkovic and Rainer Leupers, RWTH Aachen University, DE
Abstract
The involvement of third parties in the integrated circuit design and fabrication flow has introduced severe security concerns, including intellectual property piracy, reverse engineering and the insertion of malicious circuits known as hardware Trojans. Logic locking has emerged as a prominent technique to counter these security threats by protecting the integrity of integrated circuits through functional and structural obfuscation. However, this technology has been limited in its application and evaluation to small benchmark circuits, hampering the applicability in real-world scenarios. With the introduction of easy-to-access open-source RISC-V-based processor designs and their toolchain ecosystems, the evaluation of hardware security techniques on silicon-proven designs has become ever more attainable. Based on a 64-bit RISC-V core, in this work we present a holistic framework for scaling logic locking schemes to common multi-module hardware designs, thereby showcasing an industry-ready pathway of applying logic locking in a realistic design flow.
Biography
Dominik Sisejkovic received the B.Sc. and M.Sc. degree in computing (software engineering and information systems) from the Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia, in 2014 and 2016 respectively. In September 2016, he started working as a Ph.D. student and research assistant at the Institute for Communication Technologies and Embedded Systems. Since September 2017, he is working as the Technical Project Officer of the EU-funded project TETRAMAX; facilitating technology transfer from academia to European SMEs. From October 2018, he is the Chief Engineer of the Chair for Software for Systems on Silicon. His research interest includes hardware security, secure processor design and machine learning for security. In addition, he was directly involved in the design and implementation of the logic locking framework that was applied for the production of the first logic locked RISC-V processor core on the market.
