Christoph Heer, Infineon
Abstract:
Continuous cost reduction is essential for successful semiconductor business. Technology scaling supports the reduction of variable product cost, but brings many new challenges with every technology node as chip designers are facing new failure types and even higher failure probabilities. While the application level including software and firmware may further increase the failure probability, it also provides additional means to address them. This is an increasing challenge especially for safety applications like in the automotive industry due to the strict separation of hardware and software development. This presentation will address the fundamental failure mechanisms and propose a paradigm shift in design methodology to address the robustness of future highly complex systems on chips.
Curriculum Vitae
Dr. Christoph Heer, Senior Director at Infineon Technologies, is responsible for “Digital IP and Re-use” of standard components for large scale integrated digital circuits. This includes the definition of the technical roadmaps for future advanced CMOS technologies and the development of a design environment for manufacturing technologies from 180nm down to 65nm. He is also responsible for a global organisation with teams in Sophia Antipolis (France), Bangalore (India) and Munich (Germany).
Dr. Heer received a Diploma degree in solid state electronics from Aachen University of Technology in 1990 and a Ph.D. degree in electrical engineering from Ulm University in 1995. Dr. Heer has published more than 50 papers in peer-reviewed international journals and conferences. He has been member of the technical program committees of various international conferences including DAC, DATE and ASYNC.
