RISC-V Scale4Edge Ecosystem - Motivation and Objectives

Printer-friendly versionSend by emailPDF version

Wolfgang Ecker, Scale4Edge Project Coordinator, Infineon Technologies, DE


RISC-V reached its 10th anniversary this May. It evolved in this decade as a de-facto standard ISA, being widely supported by universities, the open source community, and companies. The ISA is key for compiler support and opens the door to many specializations due to its openness. As David Patterson stated: Moore’s Law is over, ushering in a golden age for computer architecture.

Many proven architectures and models are available, both commercial and as open source solutions. However, quality is not only a topic of verification but also a matter of followed, documented, and even certifiable processes. Safety and security put additional burden in terms of verification, development flow and documentation. Further, confidence in the use of software tools must be ensured and a seamless design flow must be established.

This is where the Scale4Edge project comes into place, which is introduced in this talk.


Wolfgang Ecker, Infineon Technologies, DEWolfgang Ecker is Distinguished Engineer at Infineon and Professor at Technical University of Munich. Wolfgang Ecker is (co-)author of over 200 papers on modeling and design automation, received 5 best paper awards, was granted with the German EDA achievement award. He is member of Acatech, the German Academy of Science and Engineering.

Wolfgang Ecker actively contributed and lead several successful German and European funded research projects in the area of safety, security, design automation and RISC-V based hardware innovations and related Infineon innovation activities.

Wolfgang Ecker leads the Infineon Deep Learning internal think tank. In addition, he is member of the AI commission of inquiry of the German Government.