Sigma65: Technology­based Modeling and Analyzing Methods considering variation in the 65nm node

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The topic of the investigations planned over the next years will be the introduction and full deployment of next generation technologies in digital IC design. This includes for instance the 65-nm node. Resulting from decreasing structures, new relations between the components of a chip and its environment have to be taken into consideration. The growing level of uncertainties of key parameters within a chip and between different chips in the sub-100 nm area plays a more and more important role. The process spreads have to be consequently considered in the design process. The project especially takes the description levels into account that are closely related to the process technologies. During the project period, procedures and methods will be developed that allow to determine probability distributions of parameters that describe circuits at a higher level of abstraction (gate or block level) based on the distributions of the process and transistor level parameters. The high level models shall directly depend on the main technology uncertainties as accurate as necessary.

Project coordination:

Fraunhofer Institut für Integrierte Schaltungen (IIS)
Dr.-Ing. Manfred W. Dietrich
fon: +49 351 4640-715
manfred [dot] dietrichateas [dot] iis [dot] fraunhofer [dot] de

Project partners:

Research partners:

Funding initial:

BMBF F&E 01M3080


October 01, 2006 - December 31, 2009


Project Information

Final Report
NL 04 2009 (PSB)
NL 04 2008 (PB)
NL 02 2008 (PKB)
NL 04 2007 (PN)
NL 04 2006 (PN)

Used Abbreviations

PRProject Report
SPRShort Project Report
PNProject News
FPRFinal Project Report