MAYA: New Methods for High­Volume Massive Parallel Testing, Yield Learning and High Quality

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Until 2008 digital circuitry will increase up to nearly 100 million gate equivalences; that will result in about 4 times more test vec-tors than required today. The costs of testing these new ICs and their huge data volume produced will add up to at least a factor of three, the required test time to a factor of 10. Even if not considering the increased number of pins, test cost per IC will explode to a factor of 120. The project MAYA will address this challenge by developing and integrating innovative technology for capturing data massively in parallel on-chip as well as multisite testing, and fast data processing to off-chip. These solutions will meet the demand for the next higher through-put increase of high-volume production testing at high quality.

Project coordination:

Infineon Technologies AG
Dr. Frank Pöhl
fon:

Project management:

Mentor Graphics Development (Deutschland) GmbH
Jürgen Schlöffel
fon: +49 40 79012 808
juergen_schloeffelatmentor [dot] com

Project partners:

Research partners:

Funding initial:

BMBF F&E 01M3172

Runtime:

June 01, 2006 - May 31, 2009

Website:

Project Information

Final Report
NL 03 2008 (PB)
NL 04 2007 (PKB)
NL 04 2006 (PKB)
NL 04 2006 (PN)

Used Abbreviations

AbbreviationMeaning
PRProject Report
SPRShort Project Report
PNProject News
FPRFinal Project Report