HONEY: Methods for analysis and design optimization of yield and reliability of complex ICs fabricated in leading edge technologies

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Achieving a fast product ramp, high yield and the required product reliability at the first design release are mandatory to ensure an economic manufacturing of highly complex ICs in leading edge technologies such as 65nm and below. Therefore yield and reliability aspects have to be considered already during the design phase of an integrated circuit. The main objectives of the HONEY project are to investigate and to provide abstract models, methods for circuit and system analysis, and systematic approaches to optimize yield and reliability of complex ICs in the areas of communication, automotive and industrial applications. The transfer of these methods to a potential design flow is the key step towards productive designs. Together with conventional methods for yield and reliability management this will enable product designers already in the concept and architectural planning phase of a new product development to consider cost sensitive yield and reliability aspects.

Classification in the edaMatrix:

HONEY in the edaMatrix

Project coordination:

Infineon Technologies AG
Georg Georgakos
fon: +49 89 234-24181
georg [dot] georgakosatinfineon [dot] com

Project partners:

Research partners:

Funding initial:

BMBF F&E 01M3184
MEDEA+ 2A713


December 01, 2007 - November 30, 2010



Project Information

NL 03 2009 (PB)
NL 04 2008 (PN)
NL 03 2008 (PKB)

Used Abbreviations

PRProject Report
SPRShort Project Report
PNProject News
FPRFinal Project Report