FEST: Functional Verification of Systems

Printer-friendly version Send by email PDF version

The semiconductor and chip industry are forming a market where functional requirements, complexity, time to market, cost pressure and shorting-living products are increasing dramatically. To compete in this market, a qualified verification process with short turnaround times is a key figure especially in markets with strong requirements regarding security and reliability of SoCs. The miniaturization of SoCs comes along – beside several advantages – with new challenges and questions in the design process that lead to technical and economic risks.

The aim of the FEST project is to research solutions for the unifi-cation of the SoC verification process by closing verification gaps from system level down to electric level. In this project, promising solutions are clustered to vision a coherent verification process. By using these new verification methodologies in future, the risks of re-design can be reduced, the time to market can be shortened or even a protection of market share can be achieved. Additionally, SoCs with more complexity then can be verified by formal methods.

Classification in the edaMatrix:

FEST in the edaMatrix

Project coordination:

edacentrum GmbH
Dr. Volker Schöber
fon: +49 511 762-19688

Research partners:

Supported by industry partners:

Funding initial:

BMBF CF 01M3072


July 01, 2004 - June 30, 2007



Project Information

Final Report
NL 03 2007 (PN)
NL 04 2006 (PN)
NL 03 2006 (PN)
NL 03 2006 (PB)
NL 01 2006 (PN)
NL 04 2005 (PN)
NL 03 2005 (PN)
NL 02 2005 (PN)
NL 03 2004 (PN)

Used Abbreviations

PRProject Report
SPRShort Project Report
PNProject News
FPRFinal Project Report