ASDESE: Application specific design for ESD and substrate effects

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Due to decreasing feature sizes, growing complexity, and higher operating frequencies in successive integrated circuit generations, electrostatic discharge (ESD) and substrate coupling are becoming increasingly problematic. Eliminating these effects can be very costly and time-consuming if their influence is only detected after the first wafers have been processed. This project is therefore developing methodologies to simulate the influence of ESD and substrate effects during the design phase. Designers will be able to apply the necessary corrections or integrate protective measures at this stage instead of redesigning the circuits after a costly silicon learning cycle. This will make chips inherently more reliable and robust, and make it possible to reduce the time-to-market for new developments.

Project coordination:

Robert Bosch GmbH
Dr. rer. nat Wolfgang Wilkening
fon: +49 7121 35-1533
wolfgang [dot] wilkening2atde [dot] bosch [dot] com

Project partners:

Funding initial:

BMBF F&E 01M3053
MEDEA+ T102

Runtime:

March 01, 2001 - June 30, 2003

Website:

Project Information

Final Report
Project Flyer (DE)
NL 03 2004 (PB)
NL 01 2004 (PN)
NL 02 2002 (PN)
NL 01 2002 (PN)

Used Abbreviations

AbbreviationMeaning
PRProject Report
SPRShort Project Report
PNProject News
FPRFinal Project Report