HONEY: Methods for analysis and design optimization of yield and reliability of complex ICs fabricated in leading edge technologies

Achieving a fast product ramp, high yield and the required product reliability at the first design release are mandatory to ensure an economic manufacturing of highly complex ICs in leading edge technologies such as 65nm and below. Therefore yield and reliability aspects have to be considered already during the design phase of an integrated circuit. The main objectives of the HONEY project are to investigate and to provide abstract models, methods for circuit and system analysis, and systematic approaches to optimize yield and reliability of complex ICs in the areas of communication, automotive and industrial applications. The transfer of these methods to a potential design flow is the key step towards productive designs. Together with conventional methods for yield and reliability management this will enable product designers already in the concept and architectural planning phase of a new product development to consider cost sensitive yield and reliability aspects.

Classification in the edaMatrix:

Used Abbreviations