Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study

Authors: Hoang Minh Le, Universität Bremen, DE; Vladimir Herdt, Universität Bremen, DE; Daniel Große, Universität Bremen, DE; Rolf Drechsler, Universität Bremen, DE


SystemC-based Virtual Prototypes (VPs) serve as reference models for various activities in the modern design flow and therefore, the functional correctness of each individual components and the VPs as a whole should be subjected to rigorous formal verification. In the last few years, notable progress on SystemC formal verification has been made. This paper presents a case study on applying a recent approach to formally verify TLM peripheral models. To the best of our knowledge, this is the first formal verification case study targeting this important class of VP components. First, we show how to bridge the gap between the industry-accepted modeling pattern for TLM peripheral models and the semantics currently supported by SystemC formal verification approaches. Then, we report verification results for the interrupt controller of the LEON3-based SoCRocket VP used by the European Space Agency and reflect on our experiences and lessons learned in the process.

Publication Date: 2016/03/14

Location of Publication: In Design, Automation and Test in Europe (DATE), Dresden, DE, 2016

Keyword: Verification