Compiled Symbolic Simulation for SystemC

Authors: Vladimir Herdt, Universität Bremen, DE; Hoang Minh Le, Universität Bremen, DE; Daniel Große, Universität Bremen, DE; Rolf Drechsler, Universität Bremen, DE


Ensuring the correctness of SystemC virtual prototypes is indispensable. For such models, existing symbolic simulation approaches are based on interpreting their behavior. In this paper we propose a major enhancement called Compiled Symbolic Simulation (CSS). For more scalable state space exploration, CSS augments the DUV to integrate the symbolic execution engine and the Partial Order Reduction based scheduler. Then, a standard C++ compiler is used to generate a native binary, whose execution performs exhaustive verification of the DUV. An extensive experimental evaluation demonstrates the potential of our approach.

Publication Date: 2016/11/07

Location of Publication: International Conference on Computer Aided Design (ICCAD) 2016, Austin, US

Keyword: Verification