Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation

Authors: Hoang Minh Le, Universität Bremen, DE; Rolf Drechsler, Universität Bremen, DE


Constrained randomization and functional coverage are two major pillars of the Universal Verification Methodology (UVM), which is now also available for SystemC. In this paper, we present a novel implementation of randomization and coverage for SystemC. This implementation improves the current state-of-the-art in various ways: better usability for randomization based on modern C++ syntax, more flexible coverage models, and for the first time in SystemC-based verification, coverage-driven generation is available to automate coverage closure. Our approach automatically integrates uncovered coverage bins into the stimuli model as additional constraints, which enable the underlying constraint solver to generate values filling these coverage holes directly. Experiments on a practical verification scenario show that coverage closure is achieved much faster with our approach.

Publication Date: 2015/11/11

Location of Publication: Design and Verification Conference and Exhibition Europe (DVCon Europe), Munich, DE

Keyword: Verification