SystemC-based Multi-level Error Injection for the Evaluation of Fault-tolerant Systems

Authors: Daniel Müller-Gritschneder, Technische Universi...; Ulf Schlichtmann, Technische Universität Münche...; P. R. Maier, Technische Universität München, DE; M. Greim, Technische Universität München, DE; Marc Schlichtmann, Technische Universität München, DE


Hardware faults in electronic components are a major concern especially for safety critical systems. In this paper we present an approach, which is based on simulation-based error injection and system prototypes modeled in SystemC. The target of the approach is the realization of an efficient multi-level error effect simulation for the evaluation of the fault-tolerance of a system. We run a combination of fault injection at register transfer level (RTL) and error injection at behavioral level. At RTL, novel non-intrusive fault injectors are used to inject bit flips into the registers of an embedded processor. At the behavioral level, errors are directly injected into the variables of the embedded SW and SW scheduler. This increases the significance of the results because fault masking is avoided at behavioral level. Also more and longer scenarios can be simulated because behavioral level simulation is much faster than RTL simulation. This is illustrated for a case study of an embedded control system with fail-silent recovery scheme.

Publication Date: 2014/12/10

Location of Publication: International Symposium on Integrated Circuits (ISIC), Singapore, SG

Keywords: Security; Semiconductors; Verification