Semi-Hierachical Layout Approaches for ASIC Designs with Multi-Million Instances
Technical Session 1
The Deep Submicron Hell of Physical Design
Markus Bühler, ASIC Design CenterIBM Microelectronics
During the last years multi-million transistor ASICs with several millions instances have become common. Due to shrinking technology the silicon space on a chip enables more and more System-on-a-chip (SOC) designs. From a physical design point of view these designs often consists of two design levels:
First, the “Functional Unit Level”, containing either fixed size (custom-) macros or Random Logic Macros (RLMs), which are synthesized independently and therefore are heavily interconnected. Apart from that, these units usually are loosely attached to the remaining logic. Second, the “Chip Top Level” in which the interconnections of Functional Units are done and in which the connection to the outside world is built.
In the past, two major approaches have been established to layout such chips: hierarchical and flat design styles. While the former allows for very quick turn-around-times (TAT) by divide and conquer strategies, the latter minimizes design and manpower overhead and usually results in better overall solutions.
In contrast to most other companies in the industry IBM has favoured the flat approach so far. However, on some of our latest multi-million transistor instances designs IBM has developed methodologies to incorporate hierarchical elements into our flat approach to reduce the increasing TAT while preserving the major advantages of a full flat approach. In this talk these methods and the experiences that have been gained by applying them on some of the largest ASICs in the industry will be presented.
Markus Bühler was born in 1967 at Offenburg/Germany. He studied Electrical Engineering at the University of Karlsruhe from 1987 to 1993. After various industry positions he was research assistant at the University of Stuttgart in the area of Low Power Design. Since 1999 he works in the field of physical design at IBMs ASIC Design Center in Boeblingen. Markus Buehler graduated as Dr. rer. nat. from the University of Stuttgart in the year 2000.