Manufacturability Profiling of IC Designs: Obvious and Not So Obvious Manufacturability Design Attributes
Wojciech Maly, Professor of Electrical and Computer Engineering Carnegie Mellon University
Manufacturability of an IC is a notion which seems to be well understood. It is usually characterized in terms of predicted yield loss for a given design. But in reality, yield predictions are feasible only for a fraction of phenomena which cause IC failures. Also yield loss is not a number – it is a function of time. As a result, IC designers as well as CAD tools use “intuitive manufacturability indicators“ instead of yield estimates. For example these include pattern density, number of vias and few other similar figures to guide design and CAD tools. The purpose of this talk is to analyze whether these “manufacturability indicators“ are sufficient to achieve producible designs. Additionally in this talk a research agenda will be formulated, which will enhance the currently used portfolio of manufacturability indicators.
Wojciech Maly received the Ph.D. degree from the Institute of Applied Cybernetics, Polish Academy of Sciences, in 1975. In 1975, he was appointed Assistant Professor at the Technical University of Warsaw. From September 1979 to July 1981, he was a Visiting Assistant Professor of Electrical and Computer Engineering at Carnegie Mellon University, where he has become the Whitaker Professor of Electrical and Computer Engineering.
Dr. Maly‘s research interests have been focused on the interfaces between VLSI design, testing and manufacturing with the stress on the stochastic nature of phenomena relating these three VLSI domains. He has authored, co-authored and edited a number of books, journal and conference papers as well as patents, promoting the integration of design, test and manufacturing.
Dr. Maly was elected an IEEE Fellow in 1990 and has been recipient or co-recipient of various awards including honors for his Ph.D. thesis and the Eta Kappa Nu CMU Sigma Chapter Excellence in Teaching Award.