Current and Future RISC-V Activities for Virtual Prototyping and Chip Design

Authors: Peer Adelt, Universität Paderborn, DE; Bastian Koppelmann, Universität Paderborn, DE; Wolfgang Müller, Universität Paderborn, DE

Abstract:

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Publication Date: 2018/06/21

Location of Publication: Presentation at the RISC-V Workshop, Munich, DE

Keywords: RISC-V; Virtual Prototype