State-of-the-art (technical background)


Electronic Design Automation (EDA) is a key factor for fast and efficient development of complex mixed-signal/mixed-domain systems. The ultimate goal of EDA is to provide a comprehensive top-down design method with secured constraint propagation between all design steps from system definition down to integrated-circuit mask generation. In this respect, the techniques and tools that are available today for the design of analog and mixed-signal components are lagging considerably behind the ones from the digital domain. Therefore, as soon as a system includes some analog functions, EDA efficiency and comprehensiveness are dramatically reduced. Yet, real life is analog: microphones and antennas in a wireless phone or sensors in an automobile deliver analog signals that are processed in their analog form before being converted by an analog device to the digital world. A complete electronic system almost always involves analog blocks, and, clearly, EDA should cope with that fact.


Mixed-Signal Systems: Simulation and Top-Down Design

Present Situation

The simultaneous design of both digital and analog system components requires significant extensions of currently available methods and tools. The very advanced methods used in the design of digital circuits (system partitioning, logic synthesis, layout synthesis) must be combined with the methods used in analog circuit design (topology selection, sizing, layout) to produce an efficient and effective overall methodology. While specialized EDA tools are already available for many individual design stages, no satisfactory solutions exist yet for performing the step from one level to the next and for system simulations with mixed abstraction levels. Actually, tools such as Matlab, Cossap, Saber, or Mathematica as well as modeling languages such as VHDL, VHDL-AMS or C/C++ can be used for either system or block design but, currently, not for both at the same time. On the one hand, this is due to the lack of interfaces between tools used on different levels. On the other hand, the listed languages and tools do not have the capabilities needed for the description and simulation of all required levels. Moreover, standards like VHDL-AMS have only recently matured. Thus, they did not have a noticeable effect on today’s design practice, yet. As these standards have been set only for the first time, these languages still lack important capabilities (like frequency domain or synthesis and sizing support in case of VDHL-AMS).

Proposed Innovation

The consortium intends to overcome these deficiencies by providing extensions to existing modeling languages, new simulation algorithms, and computing environments for a seamless top-down, system-on-chip design method with mixed-level simulation support. They will result in enhanced or even new tools significantly speeding up the design process. The insights to be gained from within this project will be used to influence international standardization efforts.


Circuit Synthesis and Automated Behavioral Modeling Techniques

Present Situation

Analog circuit design on the block level comprises three main steps: topology creation/selection, sizing, and design centering. Today, topologies are mostly designed manually with a schematic editor or selected from a (fixed) topology database; there is still little CAD support for generating new topologies. On the other hand, major progress in EDA for interactive circuit sizing has been made in the SADE project. Yet, a number of important problems, such as sizing with respect to noise or RF characteristics, are still on the agenda.

After nominal design, design centering is usually applied to increase the yield. Current design centering tools incur high initialization costs due to the time-consuming data preparations needed for a centering run. Moreover, the time and cost factor of worst-case calculations using Monte Carlo simulations is unreasonably high with today’s design complexities. Another challenge is posed by local parameter variations (e.g. mismatch); their influences increase strongly in the deep sub-micron range. There are currently no satisfactory solutions for analyzing these influences or for their optimization using statistical or deterministic methods.

Behavioral models play an important role in modern circuit design. They serve as executable specifications in top-down system design and as abstract descriptions of functional blocks needed for a reuse-oriented design style. Traditionally, behavioral models are coded manually. As this is a time-consuming task, the level of automation needs to be increased. Methods for automated model generation have been developed in the SADE project; however, as of now, only small-signal and DC behavior can be modeled automatically. Moreover, the optimal generation of HDL templates from model equations for best simulation performance is still an open issue.

Proposed Innovation

After the successful development of sizing methods for analog circuits in SADE, the focus in ANASTASIA+ will be on computer methods for interactive synthesis of circuit topologies. The aim is to develop a concept for determining the target function to be implemented and for capturing the corresponding design constraints. The sizing tool from SADE will be adapted to the requirements for circuit synthesis and extended to new circuit classes (e.g. RF applications). Further efforts will be made to take into account technology variations in the sizing process.

To improve the acceptance and efficiency of design centering, user-friendly procedures for setting up and interacting with design centering tools will be provided. Available methods for determining worst-case and best-case parameters will be enhanced. New methods for calculating the influence of local parameter variations as well as for interactively estimating the effect of changing component values on circuit performance and yield will be developed.

In the field of behavioral modeling, concepts and methods for computer-aided modeling of nonlinear dynamic circuits as well as for describing environmental and low-level effects will be developed. Emphasis will be put on techniques for generating behavioral models optimized for simulation performance. To support top-down design and language-based behavioral simulation, template generators for different mixed-signal HDLs will be provided.


Reuse Environment and Layout for Reuse

Present Situation

Reuse methods – particularly for digital blocks – have already advanced from the research domain far into the application domain. The partners can draw upon their own results and experiences gained from the MEDEA projects EURIPIDES and SADE, in which largely formalized mechanisms have already been investigated in the digital area and flexible search methods developed for the analog area. However, there are still many challenges to be solved in the analog and mixed-signal circuits domain, mainly as a result of the absence of language-based design methods (top-down design, circuit synthesis) and the impossibility of a '1:1' reuse. This has led to a situation in this sector in which there is still a considerable lack of well-documented examples of reusable blocks. Similarly, there has been scarcely any investigation of the degree of reuse in newly designed ICs. In the area of layout generation, previous work in projects like JESSI-AC12 and others focused primarily on layout synthesis and layout compaction methods.

Proposed Innovation

Concepts for web-based model documentation and reuse library platforms will be investigated. The results will be compiled and implemented in a prototype of a web-based reuse library environment which will include library elements needed for the demonstrator applications. To automate the reuse driven layout generation, the usage of re-synthesis and compaction to adapt existing layout will be evaluated. The work aims to the integration of web-based model documentation and the developed layout generators as a design reuse platform into the industrial design flows.