Overview (Executive Summary)


Design automation for analog/mixed-signal (A/MS) circuits and systems is still lagging behind compared to what has been reached in the digital area. As System-on-Chip (SoC) designs include analog components in most cases, these analog parts become even more a bottleneck in the overall design process. The goal of this project is to achieve a significant improvement in design automation for these A/MS parts, covering the complete system environment. A major step will be to close the current gap in the industrial design flow between system specification and design on the one hand and block-level circuit design on the other hand. Seamless top-down design methods for integrated analog and mixed-signal systems will be developed as well as tools and methods to achieve a high level of automation and reuse in the A/MS design process.

The focus of the project work will be on applications in the area of automotive electronics, data communications and wireless telecommunications. An important goal of the activities is the creation of a seamless and tool-supported design method for sigma-delta converters as these play a crucial role in most application areas covered by this proposal.

The composition of the consortium, with partners and subcontractors from the fields of system/semiconductor manufacturers, universities, applied research institutes, and CAD providers, enables improvements in EDA to be realized which specifically target the relevant applications.

The project deliverables - methods, models, tools and demonstrators - will make complete, tool-supported top-down A/MS design flows possible, aiming at a breakthrough in mixed-signal design methods, resulting also in the next generation of commercial A/MS design tools. Moreover, as A/MS design will continue to mature throughout the project duration, the consortium aims at significantly influencing international standards through bodies like VSIA and/or IEEE.

The results of the project will have a significant influence on the design capability for the above-mentioned application areas: design efficiency as well as the probability to have first-time-right-silicon for SoCs will strongly increase because a seamless design and verification flow will be provided. Project results like automated modeling and sizing tools as well as layout synthesis methods will be the key elements for improving the reusability of analog functional blocks. This will strongly decrease design time and, at the same time, increase design security.