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Please contact us at , if you would like us to send the printed program booklet to you by mail.
| Welcome and Keynote Moderator: W. Rosenstiel (edacentrum) |
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|---|---|---|
| 10:00 | Welcome | H. Bossy (BMBF) |
| 10:15 | System-level Design Technologies for Heterogeneous Distributed Systems | G. De Micheli (EPFL) |
| 11:00 | Coffee Break | |
| Technical Session: System Level Design Moderator: F. Petrot (TIMA) |
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| 11:30 | Integrated Analog-Digital HW/SW Co-Design | N. Bannow (Bosch) |
| 12:05 | Industrial Experience with System Level Design | M. Martinez (DS2) |
| 12:30 | TSAR: Virtual Prototyping of a Scalable Multi-core Architecture | A. Greiner (U Pierre et Marie Curie) |
| 12:55 | Q&A | |
| 13:00 | Lunch | |
| Technical Session: 3D Integration Design & Technology Moderator: M. Diaz-Nava (STMicroelectronics) |
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| 14:00 | Potentials of 3D Integration Technology and Challenges for Design Support | J. Weber (Fraunhofer IZM) P. Schneider (Fraunhofer IIS/EA) |
| 14:35 | 3D Technologies and Data Structures – An Overview |
R. Fischbach (TU Dresden) |
| 15:00 | CAD Tools and Design Flow for 3D Integration | L. McIlrath (R3Logic) |
| 15:25 | Q&A | |
| 15:30 | Coffee Break | |
| Session: LOMOSA/COMCAS Low Power Solutions Moderator: R. Locatelli (STMicroelectronics) |
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| 16:00 | A Power Aware Transactional Level Multiprocessor Soc Simulation Environment | F. Petrot (TIMA) |
| 16:35 | Novel Method for Power Optimization in Cellular Baseband Circuits | D. Mueller (ST Ericsson) |
| 17:00 | Power-Efficient Routing Implementation in Heterogeneous On-chip Networks | J. Flich (U Politecnica de Valencia) |
| 17:25 | Q&A | |
| Panel Moderator: J. Borel (J.B - R&D) |
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| 17:30 | TSV (Through Silicon Via) Technology as a Driver for ESL Design Solutions? The purpose of the panel is to discuss the importance of an ESL concurrent design solution to develop better early optimized products versus present TSV designs using only a bottom up approach. |
A. Asenov (U Glasgow) D. Henoff (STMicroelectronics) R. Locatelli (STMicroelectronics) |
| 18:30 | Break | |
| Conference Dinner | ||
| 19:30 | Meeting point at hotel reception | |
| 19:45 | Arrival at "Italien Village" | |
| 20:00 | Dinner | |
| 23:00 | End of 1st day | |
| Keynote Moderator: J. Haase (edacentrum) |
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|---|---|---|
| 9:00 | 3D Integration for Multimedia Applications | D. Henoff (STMicroelectronics) |
| 9:45 | Coffee Break | |
| Technical Session: Design and Verification of Analog/Mixed-Signal Circuits and Systems Moderator: R. Popp (edacentrum) |
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| 10:10 | VeronA Paves the Way for Advanced Verification of Analog Circuits | P. Jores (Bosch) |
| 10:40 | Joint Property Specification for Transient Simulation and Formal Verification of Analog Circuits | S. Steinhorst (U Frankfurt) |
| 11:00 | SystemC-AMS for the Design of Complex Analog Mixed Signal SoC‘s | K. Einwich (Fraunhofer IIS/EAS) |
| 11:20 | Modeling Heterogeneous Systems with SystemC-AMS: Application to Wireless Sensor Network | F. Pêcheux (U Pierre et Marie Curie) |
| 11:40 | Q&A | |
| Poster Session Moderator: C. Hansen (edacentrum) |
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| 11:45 | Introduction to the Poster Exhibition including the project „Synthesis-supported Design of Analog Circuits“ (SyEnA) |
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| 12:05 | Poster Exhibition | |
| 12:30 | Lunch and Poster Exhibition | |
| Technical Session: Design for Yield Moderator: G. Georgakos (Infineon) |
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| 14:00 | Yield Optimization and Assessment Methodologies in Physical Design | H. Melzner (Infineon) |
| 14:35 | Challenges in Analog Sizing for Yield and Reliability | H. Gräb (TU München) |
| 15:00 | Waveform-based Timing Analysis for Digital Circuits Using Current Source Models and Model Order Reduction | C. Knoth (TU München) |
| 15:25 | Q&A | |
| 15:30 | Coffee Break | |
| Panel Moderator: H. Rödig (Infineon) |
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| 16:00 | R&D Ecosystem to Build the European Electrical Car | C. de Vries (NXP) J. Langheim (STMicroelectronics) B. Ponick (U Hannover) C. Sebeke (Bosch) |
| 17:30 | Break | |
| Social Event | ||
| 18:00 | Meeting point at hotel reception for guided tour | |
| 18:15 | Guided tour at "VW Transparent Factory" | |
| 19:00 | Meeting point at hotel reception | |
| 19:15 | Arrival at "Lesage" | |
| 19:30 | Award of "EDA-Medaille 2009" | |
| 19:45 | Dinner | |
| 23:00 | End of 2nd day | |
| Keynote Moderator: N. Wehn (TU Kaiserslautern) |
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|---|---|---|
| 9:00 | Function-oriented Development | K. Revermann (Volkswagen) |
| Autonomous Integrated Systems Moderator: V. Schöber (edacentrum) |
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| 9:45 | Reliability and Safety-Guarantees in Modern MPSoCs with Real-Time Requirements | M. Sebastian (TU Braunschweig) |
| 10:10 | ESL Power Estimation for Embedded Processors | B. Sander (FZI) |
| 10:35 | A Demonstration Platform for Autonomous Integrated Systems | N. Wehn (TU Kaiserslautern) |
| 11:10 | Coffee Break | |
| 11:10 | Poster Exhibition | |
| 13:00 | Lunch | |
| Test, Reliability and Validation Moderator: E. Barke (edacentrum) |
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| 14:30 | MAYA - A Significant Step for Efficient Production Testing and Faster Yield Learning | J. Alt (Infineon) |
| 15:00 | Fault-tolerant Interconnects Using Codes and Self-repair | D. Scheit (BTU Cottbus) |
| 15:30 | A Rapid Prototyping Environment for ASIP Validation in Wireless Systems | M. Alles (TU Kaiserslautern) |
| 15:55 | Closing words | E. Barke (edacentrum) |
| 16:05 | End of 3rd day | |
edacentrum | Schneiderberg 32 | 30167 Hannover | fon: +49 511 762-19699 | fax:+49 511 762-19695 | email: 
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